GC5330IZEV Datasheet, PDF (26/49 Pages) Texas Instruments – Wideband Transmit-Receive Digital Signal Processors

GC5330
GC5337
SLWS226 B – DECEMBER 2010 – REVISED JANUARY 2011
Table 8. RX BB Pin Assignments
LVDS Pair BBI[11:0]
BBOUT[0] pos. and neg.
BBOUT[1] pos. and neg.
BBOUT[2] pos. and neg.
BBOUT[3] pos. and neg.
BBOUT[4] pos. and neg.
BBOUT[5] pos. and neg.
BBOUT[6] pos. and neg.
BBOUT[7] pos. and neg.
BBOUT[8] pos. and neg.
BBOUT[9] pos. and neg.
BBOUT[10] pos. and neg.
BBOUT[11] pos. and neg.
Number of BBdata streams
Number of DDR clocks to transfer 1 complex sample
Byte Mode
BB0_DATA_0
BB0_DATA_1
BB0_DATA_2
Spare
BB0_DATA_3
BB0_DATA_4
BB0_SYNC
BB0_CLOCK
BB0_DATA_5
BB0_DATA_6
BB0_DATA_7
BB0_DATA_8
1
2
Nibble Mode
BB0_DATA_0
BB0_DATA_1
BB0_SYNC
BB0_CLOCK
BB0_DATA_2
BB0_DATA_3
BB1_SYNC
BB1_CLOCK
BB1_DATA_0
BB1_DATA_1
BB1_DATA_2
BB1_DATA_3
2
4
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Serial Mode
BB0_DATA_0
BB0_DATA_1
BB0_SYNC
BB0_CLOCK
BB1_DATA_0
BB1_DATA_1
BB1_SYNC
BB1_CLOCK
BB2_DATA_0
BB2_DATA_1
BB2_SYNC
BB2_CLOCK
3
8
BBOUT Clk 0
(if DDR Mode 0)
BBOUT Clk 0
(if DDR Mode 1 or 2)
Mode 1B
18 bit I/Q Data
9I, 9I, 9Q, 9Q
I0-O
I0-E
Q0-O
Q0-E
I1-O
I1-E
Q1-O
Q1-E
BBOUT Sync 0
In-O
In-E
Qn-O
Qn-E
I0-O
I0-E
Q0-O
Q0-E
BBOUT Data 0
Mode 1BF
16 bit I/Q Data + 4 bits gain
8I +1G, 8I + 1G, 8Q + 1G, 8Q + 1G
‘n’ can be up to 47, ‘O’ is 8 (or 9) odd numbered bits (1, 3, 5, ...), ‘E’ is 8 (or 9) even numbered bits (0, 2, 4, ...), with 0 being the LSB
I0-A
I0-B
I0-C
I0-D
Q0-A
Q0-B
Q0-C
Q0-D
BBOUT Clk 0
(if DDR Mode 0)
BBOUT Clk 0
(if DDR Mode 1 or 2)
BBOUT Sync 0
In-A
In-B
In-C
In-D
Qn-A
Qn-B
Qn-C
Qn-D
BBOUT Data 0
Modes 1N, 2N
16 bit I/Q Data
4I, 4I, 4I, 4I, 4Q, 4Q, 4Q, 4Q
BBOUT Clk 1
(if DDR Mode 0)
BBOUT Clk 1
(if DDR Mode 1 or 2)
Modes 1NF, 2NF
14 bit I/Q Data + 4 bits gain
4I, 4I, 4I, 2I +2Q, 4Q, 4Q, 4Q, 4G
BBOUT Sync 1
I0-A
I0-B
I0-C
I0-D
Q0-A
Q0-B
Q0-C
Q0-D
In-A
In-B
In-C
In-D
Qn-A
Qn-B
Qn-C
Qn-D
BBOUT Data 1
‘n’ can be up to 47, ‘A’ is 4 MSBs, ‘B’ is next 4 bits, ‘C’ is next 4 bits and ‘D’ is 4 LSBs
BBOUT ClkOUT 0
(if DDR Mode 0)
BBOUT Clk 0
(if DDR Mode 1 or 2)
BBOUT Sync 0
I0-A
I0-B
I0-C
I0-D
I0-E
I0-F
I0-G
I0-H
I0-A
I0-B
I0-C
I0-D
I0-E
I0-F
I0-G
I0-H
Qn-A
Qn-B
Qn-C
Qn-D
Qn-E
Qn-F
Qn-G
Qn-H
Qn-A
Qn-B
Qn-C
Qn-D
Qn-E
Qn-F
Qn-G
Qn-H
BBOUT Data 0
BBOUT Clk 1
(if DDR Mode 0)
BBOUT Clk 1
(if DDR Mode 1 or 2)
BBOUT Sync 1
BBOUT Data 1
BBOUT Clk 2
(if DDR Mode 0)
BBOUT Clk 2
(if DDR Mode 1 or 2)
BBOUT Sync 2
Modes 1S, 2S, 3S
16 bit I/Q Data
4I, 4I, 4I, 4I, 4Q, 4Q, 4Q, 4Q
Modes 1SF, 2SF, 3SF
14 bit I/Q Data + 4 bits gain
4I, 4I, 4I, 2I +2Q, 4Q, 4Q, 4Q, 4G
I0-A
I0-B
I0-C
I0-D
I0-E
I0-F
I0-G
I0-H
Qn-A
Qn-B
Qn-C
Qn-D
Qn-E
Qn-F
Qn-G
Qn-H
BBOUT Data 2
‘n’ can be up to 47, ‘A’ is 2 MSBs, ‘B’ is next 2 bits, ‘C’ is next 2 bits, ... and ‘H’ is 2 LSBs
T0505-01
Figure 13. RX BB Formats
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