GC5330IZEV Datasheet, PDF (27/49 Pages) Texas Instruments – Wideband Transmit-Receive Digital Signal Processors

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GC5330
GC5337
SLWS226 B – DECEMBER 2010 – REVISED JANUARY 2011
Capture Buffers
The GC533x has two capture buffers, each 4096 complex words (18-bits I, 18-bits Q) deep, which are
periodically read by the external coefficient update controller (DSP) in order to optimize the DPD coefficients. The
capture buffers can be configured to sample data signals at the following points in the GC533x:
● DPD HP mode input
● DPD HP mode output
● DPD HB mode input
● DPD HB mode output
● RX AB input
● RX path 0/1 output
● RX C (feedback) input
● Testbus
(Referred to as node A)
(Node B)
(Node C)
(Node D)
(Node E)
(Node F)
(Node G)
The capture buffers can be triggered via an external sync signal, through a software trigger, or when the
monitored signal exceeds the user-configurable thresholds. The capture buffers can be programmed to monitor
the signal statistics continuously and only capture data when certain requirements are met, as well as to
generate an interrupt when a qualified buffer is captured. This helps in selecting an optimum set of data for the
DSP to use in optimizing the DPD coefficients. The capture buffers can be read by the DSP via the MPU
interface.
The capture buffers also allow synchronized multi-chip data capture. For a multiple antenna system that uses
more than one GC533x, a feedback signal to use in adapting DPD coefficients in multiple GC533x chips can be
connected to just one of the GC533x chips. The SYNCOUT signal can be used to daisy-chain (e.g., connecting
to SYNCA on the next chip) across the GC533x chips in the system. The SYNCOUT signal indicates the end of
the data capture and can be used as a capture trigger in all chips.
Microprocessor (MPU) Interface
The MPU interface is designed to interface with external memory interface (EMIF) ports on TI DSPs operating in
asynchronous mode. It consists of a 16-bit bidirectional data bus, an 8-bit address bus, and WEB, OEB, CEB,
and EMIFENA control signals. The interface supports the TI ‘C6748 as an EMIF asynchronous interface. The
MPU interface has two address spaces: a paged address space and an auto-increment address space.
To enable the EMIF interface, pin EMIFENA must be set to logic high.
In an MPU write cycle, a GC533x internal MPUCLK signal is generated by NORing CEB and WEB. The
MPUCLK signal goes high when both CEB and WEB are asserted and goes low as soon as either CEB or WEB
is de-asserted. The MPU data is latched on the rising edge of the MPUCLK signal. For the auto-increment
address spaces, the auto-increment address increments on the falling edge of the MPUCLK signal.
In an MPU read cycle, a GC533x internal MPUCLK signal is generated by NORing CEB and OEB. The MPUCLK
signal goes high when both CEB and OEB are asserted and goes low as soon as either CEB or OEB is
de-asserted. The MPU readback data is available soon after the rising edge of the MPUCLK signal. For the
auto-increment address spaces, the auto-increment address increments on the failing edge of the MPUCLK
signal.
Figure 14 shows the MPU interface timing diagram. The timing specifications are provided in Table 26 and
Table 27.
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