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GC5330IZEV Datasheet, PDF (35/49 Pages) Texas Instruments – Wideband Transmit-Receive Digital Signal Processors
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GC5330
GC5337
SLWS226 B – DECEMBER 2010 – REVISED JANUARY 2011
Table 15. TX DAC Clock Centered Over Data Switching Characteristics (See Table 5 for Connections)
DDR LVDS
fCLK(DAC)
PARAMETER
DAC output clock frequency
See (1)
TEST CONDITIONS
MIN
MAX UNIT
620 MHz
CLOCK
TXA4
TXA14
TXA9
TXB4
TXB14
TXB9
DATA
TXA9:5, 3:0
TXA19:15, 13:10
TXA19:10, 8:0
TXB9:5, 3:0
TXB19:15, 13:10
TXB19:10, 8:0
TEST CONDITIONS
See (2) (3)
See (2) (3)
See (2) (3)
See (2) (3)
See (2) (3)
See (2) (3)
MIN
SKEW
–190
–241
–200
–169
–198
–145
MAX
SKEW
139
205
155
238
146
235
UNIT
ps
ps
ps
ps
ps
ps
(1) Chip specifications are production tested at 90°C case temperature for the given specification. Early production lots are sample tested
at –40°C.
(2) Skew measured from DAC DATA desired P/N crossing to DATA P/N crossing. A negative skew is when the data arrives prior to the
clock.
(3) tsu = 1/4 DAC clock period – Max. Skew, th = 1/4 DAC clock period + Min. Skew
Table 16. TX DAC Clock Aligned With Data Switching Characteristics (See Table 5 for Connections)
DDR LVDS
fCLK(DAC)
PARAMETER
DAC output clock frequency
TEST CONDITIONS
See (1)
MIN
MAX UNIT
620 MHz
CLOCK
TXA4
TXA14
TXA9
TXB4
TXB14
TXB9
DATA
TXA9:5, 3:0
TXA19:15, 13:10
TXA19:10, 8:0
TXB9:5, 3:0
TXB19:15, 13:10
TXB19:10, 8:0
See (2)
See (2)
See (2)
See (2)
See (2)
See (2)
TEST CONDITIONS
MIN
SKEW
–190
–241
–200
–169
–198
–145
MAX
SKEW
139
205
155
238
146
235
UNIT
ps
ps
ps
ps
ps
ps
(1) Chip specifications are production tested at 90°C case temperature for the given specification. Early production lots are sample tested
at –40°C.
(2) Skew measured from DAC DATA desired P/N crossing to DATA P/N crossing. A negative skew is when the data arrives prior to the
clock.
DAC Data, DAC Frame
DAC Data Clock
Min
Skew
Max
Skew
Max
Skew
Min
Skew
Ideal Data Placement
T0510-01
Figure 18. TX LVDS Timing Specifications (TXA and TXB) (DACCLK Centered Over Data)
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