GC5330IZEV Datasheet, PDF (39/49 Pages) Texas Instruments – Wideband Transmit-Receive Digital Signal Processors

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ADC Clock
GC5330
GC5337
SLWS226 B – DECEMBER 2010 – REVISED JANUARY 2011
ADC Frame Clock
ADC Data
t_su
t_h
t_h
t_su
T0513-01
Figure 21. RX ADC LVDS Timing Specifications (RXA and RXB)
Table 21. RXA-BB Switching Characteristics
f_CLK(BB-A)
t_su(BB-A)
t_h(BB-A)
PARAMETER
RX input clock frequency
Input data setup time on port A before
ADCA Clk transition
Input data hold time on port A after
ADCA Clk transition
TEST CONDITIONS
See ⁽¹⁾
See ^{(1) (2)}
See ^{(1) (2)}
MIN NOM MAX UNIT
250 MHz
160
ps
200
ps
(1) Chip specifications are production tested at 90°C case temperature for the given specification. Early production lots are sample tested
at –40°C.
(2) Setup and hold times apply to data and appropriate ADC Clk, respectively. Timing is measured from ADC Clk threshold crossing.
Table 22. DPD Clock and Sync A,B Switching Characteristics⁽¹⁾
f_CLK(DPD)
PARAMETER
DPD input clock frequency
f_CLK(BB)
BB internal clock frequency
t_DUTY-CYCLE
f_{CLK (JITTERRMS-DPD)}
t_su(SYNCA)
t_h(SYNCA)
t_su(SYNCB)
t_h(SYNCB)
DPD input clock duty cycle
DPD clock input jitter
Input data setup time before f_CLK↑
Input data hold time after f_CLK↑
Input data setup time before f_CLK↑
Input data hold time after f_CLK↑
TEST CONDITIONS
See ⁽²⁾
See ⁽¹⁾
See ⁽³⁾
See ⁽³⁾
See ⁽²⁾
See ⁽²⁾
See ⁽²⁾
See ⁽²⁾
MIN
40%
0.25
0.1
0.35
0.05
NOM
MAX
310
{370}
250
{290}
60%
2.5%
UNIT
MHz
MHz
ns
ns
ns
ns
(1) The PLL output ranges are 400–1000 MHz. These are configuration dependent but related to the DPDCLK frequency. The cmd5330
software automatically checks these limits when compiling a configuration.
(2) Chip specifications are production tested at 90°C case temperature for the given specification. Early production lots are sample tested
at –40°C.
(3) Specification is from the PLL specification and is not production tested.
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Product Folder Link(s): GC5330 GC5337
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