GC5316 Datasheet, PDF (62/75 Pages) Texas Instruments – HIGH-DENSITY DIGITAL DOWNCONVERTER AND UPCONVERTER

GC5316
SLWS154A − JANUARY 2004 − REVISED MARCH 2004
gainfora
U 0100
0C
gainforb
cic_auto_flush_dis
cic_flush_test
U 0100
0D
E 0100
10
E 0100
10
cic_flush_clear
serp_tran_bits
serp_tran_fsdel
serp_tran_4pin
serp_tran_fsinvl
serp_tran_clkdiv
E 0100
10
U 0100
1B
D 0100
1B
D 0100
1B
U 0100
1B
U 0100
1C
ssel_pilot
U 0120
0B
6 GC5316 Pin Description
6.1 Transmit Section Signals
SIGNAL NAME
BALL
DESIG
TYPE
txclk
K26
input
txin_0_a
T23
input
txin_1_a
U25
input
txin_0_b
T24
input
txin_1_b
U26
input
txin_2_a
W26
input
txin_3_a
V25
input
txin_2_b
U24
input
txin_3_b
V26
input
txin_4_a
Y26
input
txin_5_a
W25
input
txin_4_b
V24
input
txin_5_b
U23
input
txin_6_a
W23
input
txin_7_a
AA26
input
txin_6_b
Y25
input
txin_7_b
W24
input
txin_8_a
Y23
input
62
www.ti.com
0
16
8192 This is the unsigned gain that is multiplied
with the CDMA channel A or UMTS channel
input signal. The gain multiply is calculated as
gainfora/8192.
0
16
8192 This is the unsigned gain that is multiplied
with the CDMA channel B input signal.
12
4
0
Disables the automatic flush feature in the
CIC accumulators.
8
4
0
Forces an overflow detection in the CIC only
on a rising edge of this bit, therefore it must
be programmed to ‘0’ and then back to ‘1’ for
the edge to occur.
4
4
0
Clears an overflow error manually when set,
again only on a rising edge does this occur.
11
5
17
Number of input bits per sample−1; for 18 bits,
this is set to {10001}.
8
2
1
Delay between frame sync output and MSB of
serial data {3, 2, 1, 0}.
7
1
0
Selects 2-pin mode when cleared and 4-pin
mode when set.
0
7
50
Transmit serial interface frame sync interval in
bit clocks.
0
4
1
Transmit serial interface clock divider rate−1;
0 is full rate, and 15 divides the clock by 16.
For example, to run the serial interface at 1/4
the transmit clock, set serp_tran_clkdiv(3:0) =
0011.
4
3
0
Selects the sync source for the DUC pilot
code generator.
DESCRIPTION
Transmit clock input
DUC 0 serial in data. CDMA A: I/Q UMTS: I
DUC 1 serial in data. CDMA A: I/Q UMTS: I
DUC 0 serial in data. CDMA B: I/Q UMTS: Q
DUC 1 serial in data. CDMA B: I/Q UMTS: Q
DUC 2 serial in data. CDMA A: I/Q UMTS: I
DUC 3 serial in data. CDMA A: I/Q UMTS: I
DUC 2 serial in data. CDMA B: I/Q UMTS: Q
DUC 3 serial in data. CDMA B: I/Q UMTS: Q
DUC 4 serial in data. CDMA A: I/Q UMTS: I
DUC 5 serial in data. CDMA A: I/Q UMTS: I
DUC 4 serial in data. CDMA B: I/Q UMTS: Q
DUC 5 serial in data. CDMA B: I/Q UMTS: Q
DUC 6 serial in data. CDMA A: I/Q UMTS: I
DUC 7 serial in data. CDMA A: I/Q UMTS: I
DUC 6 serial in data. CDMA B: I/Q UMTS: Q
DUC 7 serial in data. CDMA B: I/Q UMTS: Q
DUC 8 serial in data. CDMA A: I/Q UMTS: I