GC5316 Datasheet, PDF (52/75 Pages) Texas Instruments – HIGH-DENSITY DIGITAL DOWNCONVERTER AND UPCONVERTER

GC5316
SLWS154A − JANUARY 2004 − REVISED MARCH 2004
www.ti.com
imask_rx_pmeter_lsb D
2B
imask_tx_cic
D
2C
8
8
0
Interrupt mask bits for the receive composite power
meter− 8 LSBs
0
12
0
Interrupt mask bits for overflow detection in the transmit
cics
5.1.5 General Receive Controls
These registers control the receive interface to the DDC channels
VARIABLE NAME
TYPE
PAGE
ADDRESS
LSB
POSITION
BIT
WIDTH
DEFAULT
ddc_counter_lsb D 1800
5
0
16
65535
ddc_counter_msb D 1800
6
ssel_ddc_counter U 1800
7
ddc_counter_width D 1800
7
0
16
65535
8
3
0
0
8
0
ssel_adc_fifo
U 1800
8
12
3
6
ssel_resamp
U 1800
8
8
3
0
ssel_rxsync_out
U
1800
8
4
3
0
ssel_rxin
U 1800
8
0
3
0
rate_sel
U 1800
9
14
2
0
resampler_ena
U 1800
9
13
1
0
adc_fifo_bypass D 1800
9
10
1
0
resampler_decim D 1800
9
nz_pwr_mask
D 1820
6
9
1
1
0
16
0
DESCRIPTION
32-bit interval timer common to all DDC sync
inputs. This timer may be programmed to any
interval count, and each DDC synchronization
input can select this counter as a source. This
counter increments on each RX clock rising
edge. 16 LSBs
32-bit interval timer common to all DDC sync
inputs.16 MSBs
Selects the sync source for the DDC sync
counter.
Sets the width of the counter generated sync
pulse in RX clock cycles, from 1 to 256. The
width of the the ddc_counter pulse should be set
wide enough to be asserted for an entire clock
period of the slowest block to use this sync
Selects the sync source for the adc FIFO block.
Sync reinitializes the read and write pointers of
the FIFO.
Selects the sync source for the
ADC_RESAMPLER block.
Selects the sync source for the RXSYNC_OUT
pin.
Synchronizes the rx_distribution bus source and
destination and clock generation in each of the
DDC blocks.
This selects the FIFO output rate when
adc_fifo_bypass = 0. When using the resampler,
this value should be programmed to a 0. When
set to 0, the FIFO output is clocked by rxclk
(gated if resampler is on and decimating by 1.5).
When set to 1, the FIFO output rate is 1/2 of
rxclk rate. When set to 2, the FIFO output rate is
1/4 of rxclk rate, and when set to 3, the FIFO
output is at 1/8 of rxclk rate. E.g.: With rxclk
122.88 MHz, set rate_sel to 0, 1, 2 or 3
respectively for adcclk 122.88, 61.44, 30.72 or
15.36 MHz.
When asserted turns on the ADC_RESAMPLER
block.
When asserted, the adc_fifo is bypassed. Input
data is then clocked in directly using the RXCLK
input. The ssel_rxin selection value will control
the location of the internally generated sample
clock when this bit is asserted.
This tells the ADC_RESAMPLER block the
decimation factor (1=1.5X, 0=2X)
Used along with rduz_sens_ena, it selects the
noise bits to be added to the ADC input sample
when asserted.
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