GC5316 Datasheet, PDF (41/75 Pages) Texas Instruments – HIGH-DENSITY DIGITAL DOWNCONVERTER AND UPCONVERTER

www.ti.com
VARIABLE
sumchn_sel_a(3:0)
GC5316
SLWS154A − JANUARY 2004 − REVISED MARCH 2004
Table 16. Programming
DESCRIPTION
Enable bits signal A contribution to the four sum chain outputs.
Signal A Out
0000 Signal A added to no busses
0001 Signal A I/Q to bus0
0010 Signal A I/Q to bus1
0100 Signal A I/Q to bus2
1000 Signal A I/Q to bus3
3.2
sumchn_sel_b(3:0)
Note: Signal A output can contribute to any combination of the four sumchain outputs.
The above 4-bit code can range from 0 to 15.
Enable bits for signal B contribution to the four sum chains (only when in CDMA
mode).
Signal B Out
0000 Signal B added to no busses
0001 Signal B I/Q to bus0
0010 Signal B I/Q to bus1
0100 Signal B I/Q to bus2
1000 Signal B I/Q to bus3
Note: Signal B output can contribute to any combination of the four sumchain outputs.
The above 4-bit code can range from 0 to 15.
Transmit Sum Chain Shifting and Rounding
Figure 35. Final Sum Chain Scale and Round Block
Summed data is scaled from 26 bits down to 18 bits. The desired 18 bits can be taken anywhere over the 26 bit sum
chain output window via a programmable register. These 18 bits can range from sumchain(25:8) on the top end, to
sumchain (17:0) on the bottom end of the 26 bit output.
The scaled data is then hard-limited and rounded to 18, 16, 14, or 12 bits. Rounded data is MSB justified with the
bottom bits zeroed. For example, 12-bit rounding would force the output data to the top 12 bits of the 18-bit word and
the bottom 6 bits would be zeroed.
Gain = 2^{interf_scale−5}
41