GC5316 Datasheet, PDF (22/75 Pages) Texas Instruments – HIGH-DENSITY DIGITAL DOWNCONVERTER AND UPCONVERTER

GC5316
SLWS154A − JANUARY 2004 − REVISED MARCH 2004
www.ti.com
Table 19. Programming
VARIABLE
agc_dbelow(3:0)
agc_dabove(3:0)
DESCRIPTION
Sets the value of gain step size Dblw (data × current gain below threshold). Dblw = 3 + agc_dbelow.
agc_dbelow ranges from 0 to 15.
Sets the value of gain step size Dabv (data × current gain above threshold). Dabv = 3 + agc_ dabove. agc_ dabove
ranges from 0 to 15.
agc_dzero(3:0)
agc_dsat(3:0)
Sets the value of gain step size Dzro (data × current gain consistently zero). Dzro = 3 + agc_ dzero. agc_ dzero
ranges from 0 to 15.
Sets the value of gain step size Dsat (data × current gain consistently saturated). Dsat = 3 + agc_ dsat. agc_ dsat
ranges from 0 to 15.
agc_zero_msk(3:0)
agc_thres(7:0)
agc_gaina_lsb(15:0)
agc_gaina_msb(18:16)
agc_gainb_lsb(15:0)
agc_gainb_msb(18:16)
ssel_gain(2:0)
agc_zero_cnt
agc_max_cnt
agc_md(3:0)
agc_rnd_disable
agc_freeze
agc_clear
agc_amax(15:0)
agc_amin(15:0)
gain_mon
Masks the lower 4 bits of signal data so as to be considered zeros.
AGC threshold. Compared with magnitude of 8 bits of input × gain.
Lower 16 bits of 19-bit gain word for DDC A. Requires a sync (ssel_gain) to load.
Upper 3 bits of 19-bit gain word for DDC A. Requires a sync (ssel_gain) to load.
Lower 16 bits of 19-bit gain word for DDC B (in CDMA mode). Requires a sync (ssel_gain) to load.
Upper 3 bits of 19-bit gain word for DDC B (in CDMA mode). Requires a sync (ssel_gain) to load.
Sync to update agc_gain settings. Note that both A and B are updated.
When the AGC output (input × gain) masked magnitude is zero value this number of times, the shift value is
changed to agc_dzero.
When the AGC output (input × gain) is zero value this number of times, the shift value is changed to agc_dsat.
AGC rounding. Number of output bits = 18 – agc_rnd.
AGC rounding is disabled when this bit is set.
Freezes the adaptive portion of the gain to current value.
Clears the adaptive portion of the gain.
The maximum value that gain can be adjusted up to. Top 7 bits are integer, bottom 9 bits are fractional.
The minimum value that gain can be adjusted down to. Top 7 bits are integer, bottom 9 bits are fractional.
When set, combines current AGC gain with I and Q data. The 18-bit output format thus becomes:
I Portion: 8 bits of AGC’d I data − Gain(18:11) − 00
Q Portion: 8 bits of AGC’d Q data − Gain(10:5) − Status(1:0) − 00.
Note: Bit 0 of status, when set, indicates the data is saturated. Bit 1 of status, when set, indicates the data is zero.
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