GC5316 Datasheet, PDF (18/75 Pages) Texas Instruments – HIGH-DENSITY DIGITAL DOWNCONVERTER AND UPCONVERTER

GC5316
SLWS154A − JANUARY 2004 − REVISED MARCH 2004
2.4 Receive RMS Power Meter
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I
Top
37 _Integrate 32
32
Register
RMS Power
55 bits
18
Q
Clear
pmeter_interval_ddc
pmeter_sync_delay_ddc
8
8
Transfer
pmeter_integration_ddc
16
Sync
Sync Delay
Counter
7 Bits
(in samples)
Interval
Counter
8 Bits
(in increments of
1024 samples)
Integration Time Counter
18 Bits
(in increments of 4 samples)
Interrupt
Power Measurement Time Line
Interrupt
Interrupt
Interrupt
Sync Delay
Integration Time
I nte rva l
Integration Time
Interval
Integration Time
Time
Sync
Eve nt
Inte gra tion
Start
Inte gra tion
Start
Inte gra tion
Start
Figure 15. Receive Power Meter and Timing
Each DDC channel includes an RMS power meter which is used to measure the total power within the channel
passband.
The power meter samples the I and Q data stream after the PFIR filter. Both 18-bit I and Q data are squared, summed,
and then integrated over a time determined by a programmable counter: pmeter_integration_ddc (16 bits). The
integration time is a 16-bit word which is programmed into the 18-bit counter. Integration time = 4 x
pmeter_integration_ddc + 1 (in units of a sample period or generally chip period/2).
There is a programmable 8-bit interval counter which sets the interval over which power measurements are repeated.
The timer counts in increments of 1024 samples. This allows the user to select intervals from 1 x 1024 samples up
to 256 x 1024 samples. The interval time = 1024 x pmeter_interval_ddc. The interval time must be greater than (not
equal to) the integration time.
The power measurement process starts with a sync event (ssel_pmeter). The integration starts at sync event + 3
chips + sync_delay. The 7-bit delay register permits delays from 3 to 130 samples after sync. The integration
continues until the integration count is met. At that point the top 32 bits of the 55-bit accumulator is transferred to
the read register and an interrupt is generated indicating the power value is ready to read. The interval counter
continues until the programmed interval count is reached. When reached, the integration counter and the interval
counter start over again. Each time the integration count is reached the upper 32 bits are again transferred to the
read register overwriting the previous value and sending an interrupt signifying the data is ready to be read. Failure
to read the data timely results in overwriting the previous interval measurement.
Sync ssel_pmeter starts the process. Whenever a sync is received, all the counters are reset to zero no matter what
the status.
For UMTS, I and Q are calculated and the integrated power is read. When in CDMA mode the power is calculated
for both the A and B signals, producing two 32-bit results.
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