GC5316 Datasheet, PDF (45/75 Pages) Texas Instruments – HIGH-DENSITY DIGITAL DOWNCONVERTER AND UPCONVERTER

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GC5316
SLWS154A − JANUARY 2004 − REVISED MARCH 2004
The maximum complex output rate with I and Q data on separate outputs is txclk/2 for CDMA mode and txclk for
UMTS mode. If the complex output data is interleaved on a single bus, the maximum rate is txclk/2 for both UMTS
and CDMA and the toggle rate between I and Q samples is txclk.
NOTE:The tx_clk_out signal can not be at full rate (txclk rate) if the mixer is not at full rate (for CDMA mode, the mixer
can not be at full rate). If a full-rate clock output signal is desired, the tst_clk signal can be used, with the tst_rate parameter
programmed to 0.
Table 19. Programming
VARIABLE
interf_ena(3:0)
interf_real
interf_interl
tristate(3)
tristate(2)
tristate(1)
tristate(0)
trt_rate
DESCRIPTION
When bits are set, enables the corresponding outputs. When cleared, outputs are disabled and held low.
When set, outputs are real. When cleared, outputs are complex.
When set, complex data is output interleaved.
When set, turns on tx_data_out3 outputs.
When set, turns on tx_data_out2 outputs as well as sync_tst, aflag_tst, and clk_tst.
When set, turns on tx_data_out1 outputs.
When set, turns on tx_data_out0 outputs as well as tx_iflag and tx_clk_out.
The value here controls the output clock rate on the clk_tst pin. A value of 0 gives a full rate output clock (txclk
rate), a 1 gives half rate output clock, a 3 gives 1/4th rate output clock, and so on. The number of txclk cycles
for which the clk_tst signal is high + low = 1 + tst_rate.
4 GC5316 General Control
The GC5316 is configured over a bidirectional 16-bit parallel data microprocessor control port. The control port
permits access to the control registers which configure the chip. The control registers are organized using a
paged-access scheme using six address lines. Half of the 64 addresses (address 32 through address 63) represent
global registers. The other 32 (address 0 through address 31) are paged resisters. This arrangement permits
accessing a large number of control registers using relatively few address lines.
Global address 33 is the page register. Writing a 16-bit value to this register sets the page to which future write or
read operations performed. These paged-registers contain the actual parameters that configure the chip and are
accessed by writing/reading address 0 through address 31.
Global registers (address 32 through address 63) are used to read/write GC5316 parameters that are global in nature
and can benefit from single read/write operations. Examples include chip status, reset, sync options, checksum ramp
parameters, and the page register.
4.1 Control Data, Address, and Strobes
The control bus consists of 16 bidirectional control data lines C[0:15], 6 address lines A[0:5], a read enable line RD,
a write enable line WR, and a chip enable line CE. These lines usually interface to a microprocessor or DSP chip
and is intended to look like a block of memory.
Data is written by: 1) Setting up the desired address A[0:5], 2) Setting CE low, 3) Setting the desired data on C[0:15],
and then 4) Pulsing WR low. Data is written when WR returns high.
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