GC5316 Datasheet, PDF (21/75 Pages) Texas Instruments – HIGH-DENSITY DIGITAL DOWNCONVERTER AND UPCONVERTER

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GC5316
SLWS154A − JANUARY 2004 − REVISED MARCH 2004
7
6
5
4
3
2
1
D=3
0
1
10
D=18
100
1000
10000
100000
1000000
SAMPLES
D=3
D=4
D=5
D=6
D=7
D=8
D=9
D=10
D=11
D=12
D=13
D=14
D=15
D=16
D=17
D=18
Figure 17. AGC Gain Error vs Samples
The AGC noise once the AGC has converged is a random error of amplitude ±2^−D relative to the RMS signal level.
This means that the error level is −6×D dB below the signal RMS level. At D=10 (−60 dB) the error is negligible. The
plot below shows the AGC response for vales of D ranging from 3 to 18. Error dB represents the distance the signal
level is from the desired target threshold.
The AGC is also subject to user specified upper and lower adjustment limits. The AGC stops incrementing the gain
if the adjustment exceeds Amax. It stops decrementing the gain if the adjustment is less than Amin.
The input data is received with a valid flag that is high when a valid sample is received. For complex data, the I and Q
samples are on the same data input line and are not treated independently. An adjustment is made for the magnitude
of the I sample, and then another adjustment is made for the Q sample.
The AGC operates on UMTS and CDMA data. When in UMTS mode the I and Q data are each used to produce the
AGC level. There is no separate I path gain and Q path gain. When in CDMA mode there are separate gain levels
for the signal and diversity I and Q data. The I and Q for A (or the Signal ) pair is calculated and then the I and Q
for the B (or diversity) pair is calculated.
There is a freeze mode for holding the accumulator at its current level. This puts the AGC in a hold mode using the
user-programmed gain along with the current gain_adjust value. To only use the user programmed gain value as the
gain, set the freeze bit and then clear the accumulator. When using the freeze bit, the full 25-bit output is sent out
of the AGC block to support transferring up to 25 bits when the AGC is disabled.
The current AGC gain and state can also be optionally output with the DDCs I and Q output data by setting the
gain_mon variable. When in this mode, the top 14 bits of the current AGC gain word are integrated in with the
AGC-modified I and Q output data.
Table 18. Output Data Format With Embedded AGC Gain Data
Output
I
Q
Bits(17:10)
I output data
Q output data
Bits(9:4)
Gain(10:5)
Bits(3:2)
Gain(18:11)
AGC State(1:0)
Bits(1:0)
00
00
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