GC5316 Datasheet, PDF (13/75 Pages) Texas Instruments – HIGH-DENSITY DIGITAL DOWNCONVERTER AND UPCONVERTER

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GC5316
SLWS154A − JANUARY 2004 − REVISED MARCH 2004
2.3.4 Receive Channel Delay Adjust and Zero Insertion
Figure 12. Delay Adjust and Zero Insertion
The receive channel delay adjust function is used to add programmable delays in the channel downconvert path.
Adjusting channel delay can be used to compensate for analog elements external to the GC5316 digital
downconversion such as cables, splitters, analog downconverters, filters, etc. There are two functions that need to
be considered with respect to programming the channel delay; the delay memory and the zero pad blocks. The
parameter tadj_interp_decim informs the DDC block the rate at which data is arriving on the rx_distribution bus. The
zero pad block interpolates (insert zeros) to bring the signal sample rate up to rxclk rate.
The delay memory provides up to 64 sample delay at the rx_distribution rate. Read offset (tadj_offset_coarse) is a
programmable difference between the read and write pointers to the delay memory. This provides a maximum
differential delay between channels of 64/rx_distribution_rate. At an rx_distribution rate of 61.44 MSPS the 64
memory slots in the delay memory provide an overall delay window of about 1 µs. The ssel_taj_coarse sync controls
the timing for updating the coarse offset.
The zero pad block inserts 0, 1, 3, or 7 zeros between each sample coming from the mixer bringing the sample rate
up to rxclk. The tadj_offset_fine parameter specifies when the zeros are inserted relative to the ssel_tadj_fine sync
signal. This permits a fine adjustment at the rxclk rate. The 3-bit insert offset parameter allows the zeros to be inserted
up to tadj_interp_decim (max 8) high-speed clocks after ssel_tadj_fine sync is asserted. This provides a time adjust
resolution of 1/rxclk. For UMTS and assuming a GC5316 clock frequency of 122.88 MHz, the time resolution is
3.84 MCPS / 122.88 MSPS = 1/32 of a chip. For CDMA, the resolution is 1.2288 / 122.88 = 1/100 of a chip.
VARIABLE
tadj_offseta_coarse_a5:0)
tadj_offset_coarse_b(5:0)
tadj_offset_fine_a(2:0)
tadj_offset_fine_b(2:0)
tadj_interp_decim(2:0)
ssel_tadj_fine(2:0)
ssel_tadj_coarse(2:0)
Table 13. Programming
DESCRIPTION
Read offset into the 64 element memory for the A channel DDC. Note: When tadj_offset_coarse_a = 62,
then the delay is –2. When tadj_offset_coarse_a = 63, then the delay is –1. For all other values, the
resulting delay is equal to the value.
Read offset into the 64 element memory for the B channel DDC when in CDMA mode. Note: When
tadj_offset_coarse_b = 62, then the delay is –2. When tadj_offset_coarse_b = 63, then the delay is –1. For
all other values, the resulting delay is equal to the value.
Controls the zero offset (fine adjust) for the A side of the DDC.
Controls the zero offset (fine adjust) for the B side of the DDC when in CDMA mode.
The interpolation value minus one. Valid interpolations are (1, 2, 4, or 8). Valid program values for this
parameter are (0,1,3,or 7). Same for A and B channels when in CDMA mode.
Selects the sync source for the fine time adjust
Selects the sync source for the coarse time delay adjust
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