GC5316 Datasheet, PDF (23/75 Pages) Texas Instruments – HIGH-DENSITY DIGITAL DOWNCONVERTER AND UPCONVERTER

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2.6 Receive Output Interface
rxout_X_a ^Serial
DD C Block
2 CD MA2000
or 1 U MT S C hannel
rxout_ X_ b
rxout_X _c
rxout_ X_ d
where X= 0 to 11
2 CD MA
I data CD MA A
I data CD MA B
Q data CD MA A
Q data C DM A B
GC5316
SLWS154A − JANUARY 2004 − REVISED MARCH 2004
1 UM TS
I _msb
I _msb−1
Q _msb
Q _msb−1
8-Pin Mode
U MT S
Imsb
Imsb−1
Imsb−2
Imsb−3
4
2
Sync Clkdiv Frame
Dela y
Shared between two DDC blocks,
i.e., 2k and 2k + 1, k = 0 to 5
Frame Strobe
From adjacent
DDC block
Q _msb
Q _msb−1
Q _msb−2
Q _msb−3
Figure 18. Receive Output Interface
Each DDC block has four serial output data pins. These pins are used to transfer downconverted I/Q baseband data
out of the GC5316 for subsequent processing. The usage of these pins changes depending on how the DDC block
is configured.
When the block is configured for two CDMA channels, a pair of serial data pins provides separate I and Q data output
for the two DDC channels. Word size is selectable from 4 to 25 bits with the most significant bit first. Note, carefully
the signal to pin assignment, for example that Ia is assigned to rxout_X_a and Qa is assigned to rxout_X_c.
When the DDC block is configured for a single UMTS channel, even and odd I and Q data drive the four serial pins
separately, most significant bit first.
Four serial pins each for I and Q data can be optionally employed (instead of two for I and two for Q) at half the output
rate. This would most likely be used when two DDC channels (2k and 2k + 1, k= 0 to 5) are combined to support
double−length PFIR filtering (a channel is sacrificed). Formatting for I data is then: Imsb, Imsb−1, Imsb−2, Imsb−3.
Q data formatting is: Qmsb, Qmsb−1, Qmsb−2, Qmsb−3.
Two DDC blocks share a frame strobe output pin. The frame strobe is driven high when the channel outputs another
frame of data. The frame strobe can be programmed to arrive from 0 to 3 bit clocks early via a 2-bit control parameter.
Frame interval can be programmed from 1 to 63 bits. A programmable 4-bit clock divider circuit is can be used to
specify the serial bit rate. The clock divider circuit is synchronized using a sync block discussed later in this document.
Programming the serial port clock divider requires some thought and depends upon the channel’s overall decimation
ratio, frame sync interval, number of output bits, and CDMA−UMTS mode.
In general:
The serial clock divide ratio × the frame sync interval = the total receive decimation
The relationship between the number of serial bits output, clock divide ratio, and overall decimation ratio is:
CDMA :
[overall
decimation (pser_rec_8pin
(pser_recv_clkdiv ) 1)
)
1)]
u
pser_recv_bits
)
1
UMTS : 2
[overall
decimation (pser_rec_8pin
(pser_recv_clkdiv ) 1)
)
1)]
u
pser_recv_bits
)
1
23