GC5316 Datasheet, PDF (16/75 Pages) Texas Instruments – HIGH-DENSITY DIGITAL DOWNCONVERTER AND UPCONVERTER

GC5316
SLWS154A − JANUARY 2004 − REVISED MARCH 2004
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Table 15. Programming
VARIABLE
crastsrttap_cfir(4:0)
cfir_gain
DESCRIPTION
Number of DDC CFIR filter taps is 2(crastarttap + 1)
Only ls-bit is used. CFIR gain. 0 = 2e−19, 1= 2e−18
The CFIR filter’s 18-bit coefficients are loaded in two 64 word memories. Zone 2 CFIR RAM holds the lower
2 bits of the 18 bit coefficients,. This address is specified by setting up the page register to write to Zone 2 and
upper space bit Zp. The remaining bits are specified by ZZZZZ which are GC5316 address pins. The total
address is thus ZpZZZZZ which writes to 64 locations.
The CFIR filter’s 18 bit coefficients are loaded by the software cmd5316. The user must provide a coefficient
file with one integer coefficient per line. Note that the CFIR filter coefficients are shared by the A and B
channels in CDMA mode.
2.3.7 Receive Programmable FIR Filter
The receive programmable FIR filter (PFIR) pulse shapes the baseband signal data. It does not perform any
decimation. Filter coefficient size, input, and output data size is 18 bits. A special strapped mode can be employed
for UMTS where two adjacent DDCs (2k and 2k+1, k=0 to 5) can be combined to yield a filter with twice the number
of coefficients.
The PFIR length is programmable. This permits turning off taps and saving power if short filters are appropriate. The
filter’s output data can be shifted over a range of 0 to 7 bits where it is then rounded and hard limited to 18 bits. The
shift range results in a gain that ranges from 2e^−19 to 2e^−12.
The gain of the PFIR block is:
Gain + Sum(CFIR coefficients) 2^{*19)pfir_gain} where pfir_gain ranges 0 7
The maximum PFIR filter length is a function of GC5316 clock rate and output sample rate and is limited by the
number of coefficient memory registers. The maximum number of taps is 64 and the minimum number is 28 (UMTS)
or 32 (CDMA). Lengths between these limits can be specified in increments of 4.
Subject to the above minimum and maximum values, the number of maximum taps available is:
UMTS Mode : 4
rxclk
output sample rate
Strapped Mode : 8
rxclk
output sample rate
CDMA Mode : 2
rxclk
output sample rate
The strapped mode can be employed for UMTS where two adjacent DDCs (2k and 2k+1, k=0 to 5) can be combined
to yield a filter with twice the number of coefficients. This means the GC5316 can support six UMTS DDC channels
with double-length filter coefficients. Figure 14 shows the interconnect between the two DDCs when the PFIR filters
are strapped. In strapped mode, data out of the last PFIR data delay ram in the main DDC (DDC 2k) is sent to the
adjacent secondary DDC (DDC 2k+1) PFIR as input thus forming a 128-tap delay line. Also, data received from the
adjacent PFIR summers is added into the main DDC’s PFIR sum to form the output. When using strapped mode,
set double_tap to 2 for the main (even) DDC and to 1 for the secondary (odd) DDC.
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