LM3S6753 Datasheet, PDF (568/625 Pages) Texas Instruments – Stellaris LM3S6753 Microcontroller

Signal Tables
Table 21-6. Signals by Signal Name (continued)
Pin Name
Pin Number Pin Type Buffer Type^a Description
PD1
G2
I/O
TTL
GPIO port D bit 1.
PD2
H2
I/O
TTL
GPIO port D bit 2.
PD3
H1
I/O
TTL
GPIO port D bit 3.
PD4
E1
I/O
TTL
GPIO port D bit 4.
PD5
E2
I/O
TTL
GPIO port D bit 5.
PD6
F2
I/O
TTL
GPIO port D bit 6.
PD7
F1
I/O
TTL
GPIO port D bit 7.
PE0
A11
I/O
TTL
GPIO port E bit 0.
PE1
B12
I/O
TTL
GPIO port E bit 1.
PE2
B11
I/O
TTL
GPIO port E bit 2.
PE3
A12
I/O
TTL
GPIO port E bit 3.
PF0
M9
I/O
TTL
GPIO port F bit 0.
PF1
H12
I/O
TTL
GPIO port F bit 1.
PF2
J11
I/O
TTL
GPIO port F bit 2.
PF3
J12
I/O
TTL
GPIO port F bit 3.
PG0
K1
I/O
TTL
GPIO port G bit 0.
PG1
K2
I/O
TTL
GPIO port G bit 1.
PhA0
L1
I
TTL
QEI module 0 phase A.
PhB0
L2
I
TTL
QEI module 0 phase B.
PWM0
M9
O
TTL
PWM 0. This signal is controlled by PWM Generator 0.
PWM1
G2
O
TTL
PWM 1. This signal is controlled by PWM Generator 0.
PWM2
E12
O
TTL
PWM 2. This signal is controlled by PWM Generator 1.
PWM3
D12
O
TTL
PWM 3. This signal is controlled by PWM Generator 1.
PWM4
A11
O
TTL
PWM 4. This signal is controlled by PWM Generator 2.
PWM5
B12
O
TTL
PWM 5. This signal is controlled by PWM Generator 2.
RST
H11
I
TTL
System reset input.
RXIN
L7
I
Analog RXIN of the Ethernet PHY.
RXIP
M7
I
Analog RXIP of the Ethernet PHY.
SSI0Clk
M4
I/O
TTL
SSI module 0 clock.
SSI0Fss
L4
I/O
TTL
SSI module 0 frame.
SSI0Rx
L5
I
TTL
SSI module 0 receive.
SSI0Tx
M5
O
TTL
SSI module 0 transmit.
SWCLK
A9
I
TTL
JTAG/SWD CLK.
SWDIO
B9
I/O
TTL
JTAG TMS and SWDIO.
SWO
A10
O
TTL
JTAG TDO and SWO.
TCK
A9
I
TTL
JTAG/SWD CLK.
TDI
B8
I
TTL
JTAG TDI.
TDO
A10
O
TTL
JTAG TDO and SWO.
TMS
B9
I/O
TTL
JTAG TMS and SWDIO.
TRST
A8
I
TTL
JTAG TRST.
TXON
L8
O
Analog TXON of the Ethernet PHY.
568
April 05, 2010
Texas Instruments-Production Data