LM3S6753 Datasheet, PDF (20/625 Pages) Texas Instruments – Stellaris LM3S6753 Microcontroller

Table of Contents
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PWM1 Interrupt and Trigger Enable (PWM1INTEN), offset 0x084 .................................... 512
PWM2 Interrupt and Trigger Enable (PWM2INTEN), offset 0x0C4 .................................... 512
PWM0 Raw Interrupt Status (PWM0RIS), offset 0x048 .................................................... 515
PWM1 Raw Interrupt Status (PWM1RIS), offset 0x088 .................................................... 515
PWM2 Raw Interrupt Status (PWM2RIS), offset 0x0C8 ................................................... 515
PWM0 Interrupt Status and Clear (PWM0ISC), offset 0x04C ........................................... 516
PWM1 Interrupt Status and Clear (PWM1ISC), offset 0x08C ........................................... 516
PWM2 Interrupt Status and Clear (PWM2ISC), offset 0x0CC ........................................... 516
PWM0 Load (PWM0LOAD), offset 0x050 ....................................................................... 517
PWM1 Load (PWM1LOAD), offset 0x090 ....................................................................... 517
PWM2 Load (PWM2LOAD), offset 0x0D0 ....................................................................... 517
PWM0 Counter (PWM0COUNT), offset 0x054 ................................................................ 518
PWM1 Counter (PWM1COUNT), offset 0x094 ................................................................ 518
PWM2 Counter (PWM2COUNT), offset 0x0D4 ............................................................... 518
PWM0 Compare A (PWM0CMPA), offset 0x058 ............................................................. 519
PWM1 Compare A (PWM1CMPA), offset 0x098 ............................................................. 519
PWM2 Compare A (PWM2CMPA), offset 0x0D8 ............................................................. 519
PWM0 Compare B (PWM0CMPB), offset 0x05C ............................................................. 520
PWM1 Compare B (PWM1CMPB), offset 0x09C ............................................................. 520
PWM2 Compare B (PWM2CMPB), offset 0x0DC ............................................................ 520
PWM0 Generator A Control (PWM0GENA), offset 0x060 ................................................ 521
PWM1 Generator A Control (PWM1GENA), offset 0x0A0 ................................................ 521
PWM2 Generator A Control (PWM2GENA), offset 0x0E0 ................................................ 521
PWM0 Generator B Control (PWM0GENB), offset 0x064 ................................................ 524
PWM1 Generator B Control (PWM1GENB), offset 0x0A4 ................................................ 524
PWM2 Generator B Control (PWM2GENB), offset 0x0E4 ................................................ 524
PWM0 Dead-Band Control (PWM0DBCTL), offset 0x068 ................................................ 527
PWM1 Dead-Band Control (PWM1DBCTL), offset 0x0A8 ................................................. 527
PWM2 Dead-Band Control (PWM2DBCTL), offset 0x0E8 ................................................ 527
PWM0 Dead-Band Rising-Edge Delay (PWM0DBRISE), offset 0x06C ............................. 528
PWM1 Dead-Band Rising-Edge Delay (PWM1DBRISE), offset 0x0AC ............................. 528
PWM2 Dead-Band Rising-Edge Delay (PWM2DBRISE), offset 0x0EC ............................. 528
PWM0 Dead-Band Falling-Edge-Delay (PWM0DBFALL), offset 0x070 ............................. 529
PWM1 Dead-Band Falling-Edge-Delay (PWM1DBFALL), offset 0x0B0 ............................. 529
PWM2 Dead-Band Falling-Edge-Delay (PWM2DBFALL), offset 0x0F0 ............................. 529
Quadrature Encoder Interface (QEI) .......................................................................................... 530
Register 1: QEI Control (QEICTL), offset 0x000 ................................................................................ 535
Register 2: QEI Status (QEISTAT), offset 0x004 ................................................................................ 537
Register 3: QEI Position (QEIPOS), offset 0x008 .............................................................................. 538
Register 4: QEI Maximum Position (QEIMAXPOS), offset 0x00C ....................................................... 539
Register 5: QEI Timer Load (QEILOAD), offset 0x010 ....................................................................... 540
Register 6: QEI Timer (QEITIME), offset 0x014 ................................................................................. 541
Register 7: QEI Velocity Counter (QEICOUNT), offset 0x018 ............................................................. 542
Register 8: QEI Velocity (QEISPEED), offset 0x01C .......................................................................... 543
Register 9: QEI Interrupt Enable (QEIINTEN), offset 0x020 ............................................................... 544
Register 10: QEI Raw Interrupt Status (QEIRIS), offset 0x024 ............................................................. 545
Register 11: QEI Interrupt Status and Clear (QEIISC), offset 0x028 ..................................................... 546
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April 05, 2010
Texas Instruments-Production Data