LM3S6753 Datasheet, PDF (19/625 Pages) Texas Instruments – Stellaris LM3S6753 Microcontroller

Stellaris® LM3S6753 Microcontroller
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
Register 21:
Register 22:
Register 23:
Register 24:
Register 25:
Register 26:
Register 27:
Register 28:
Ethernet MAC Threshold (MACTHR), offset 0x01C .......................................................... 453
Ethernet MAC Management Control (MACMCTL), offset 0x020 ........................................ 455
Ethernet MAC Management Divider (MACMDV), offset 0x024 .......................................... 456
Ethernet MAC Management Transmit Data (MACMTXD), offset 0x02C ............................. 457
Ethernet MAC Management Receive Data (MACMRXD), offset 0x030 .............................. 458
Ethernet MAC Number of Packets (MACNP), offset 0x034 ............................................... 459
Ethernet MAC Transmission Request (MACTR), offset 0x038 ........................................... 460
Ethernet MAC Timer Support (MACTS), offset 0x03C ...................................................... 461
Ethernet PHY Management Register 0 – Control (MR0), address 0x00 ............................. 462
Ethernet PHY Management Register 1 – Status (MR1), address 0x01 .............................. 464
Ethernet PHY Management Register 2 – PHY Identifier 1 (MR2), address 0x02 ................. 466
Ethernet PHY Management Register 3 – PHY Identifier 2 (MR3), address 0x03 ................. 467
Ethernet PHY Management Register 4 – Auto-Negotiation Advertisement (MR4), address
0x04 ............................................................................................................................. 468
Ethernet PHY Management Register 5 – Auto-Negotiation Link Partner Base Page Ability
(MR5), address 0x05 ..................................................................................................... 470
Ethernet PHY Management Register 6 – Auto-Negotiation Expansion (MR6), address
0x06 ............................................................................................................................. 471
Ethernet PHY Management Register 16 – Vendor-Specific (MR16), address 0x10 ............. 472
Ethernet PHY Management Register 17 – Interrupt Control/Status (MR17), address
0x11 .............................................................................................................................. 474
Ethernet PHY Management Register 18 – Diagnostic (MR18), address 0x12 ..................... 476
Ethernet PHY Management Register 19 – Transceiver Control (MR19), address 0x13 ....... 477
Ethernet PHY Management Register 23 – LED Configuration (MR23), address 0x17 ......... 478
Ethernet PHY Management Register 24 –MDI/MDIX Control (MR24), address 0x18 .......... 479
Analog Comparators ................................................................................................................... 480
Register 1: Analog Comparator Masked Interrupt Status (ACMIS), offset 0x000 .................................. 485
Register 2: Analog Comparator Raw Interrupt Status (ACRIS), offset 0x004 ....................................... 486
Register 3: Analog Comparator Interrupt Enable (ACINTEN), offset 0x008 ......................................... 487
Register 4: Analog Comparator Reference Voltage Control (ACREFCTL), offset 0x010 ....................... 488
Register 5: Analog Comparator Status 0 (ACSTAT0), offset 0x020 ..................................................... 489
Register 6: Analog Comparator Status 1 (ACSTAT1), offset 0x040 ..................................................... 489
Register 7: Analog Comparator Control 0 (ACCTL0), offset 0x024 ..................................................... 490
Register 8: Analog Comparator Control 1 (ACCTL1), offset 0x044 ..................................................... 490
Pulse Width Modulator (PWM) .................................................................................................... 492
Register 1: PWM Master Control (PWMCTL), offset 0x000 ................................................................ 501
Register 2: PWM Time Base Sync (PWMSYNC), offset 0x004 ........................................................... 502
Register 3: PWM Output Enable (PWMENABLE), offset 0x008 .......................................................... 503
Register 4: PWM Output Inversion (PWMINVERT), offset 0x00C ....................................................... 504
Register 5: PWM Output Fault (PWMFAULT), offset 0x010 ................................................................ 505
Register 6: PWM Interrupt Enable (PWMINTEN), offset 0x014 ........................................................... 506
Register 7: PWM Raw Interrupt Status (PWMRIS), offset 0x018 ........................................................ 507
Register 8: PWM Interrupt Status and Clear (PWMISC), offset 0x01C ................................................ 508
Register 9: PWM Status (PWMSTATUS), offset 0x020 ...................................................................... 509
Register 10: PWM0 Control (PWM0CTL), offset 0x040 ....................................................................... 510
Register 11: PWM1 Control (PWM1CTL), offset 0x080 ....................................................................... 510
Register 12: PWM2 Control (PWM2CTL), offset 0x0C0 ...................................................................... 510
Register 13: PWM0 Interrupt and Trigger Enable (PWM0INTEN), offset 0x044 .................................... 512
April 05, 2010
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