LM3S6753 Datasheet, PDF (437/625 Pages) Texas Instruments – Stellaris LM3S6753 Microcontroller

Stellaris® LM3S6753 Microcontroller
and Ethernet MAC Individual Address 1 (MACIA1) registers. However, the Ethernet receiver can
also be configured for Promiscuous and Multicast modes by setting the PRMS and AMUL bits in the
MACRCTL register.
16.2.1.5
Packet Timestamps
For applications requiring very high-precision synchronization packets, the Ethernet Controller
provides a means of generating precision timestamps in support of the IEEE Precision Time Protocol
(IEEE-1588). This feature is enabled by setting the TSEN bit in the Ethernet MAC Timer Support
(MATCS) register. Note that when this feature is enabled, General-Purpose Timer 3 (GPT3) must
be dedicated to the Ethernet Controller. GPT3 must be configured to 16-bit edge capture mode,
see page 234. Timer A of GPT3 stores the receive time, and Timer B stores the transmit time. One
other General-Purpose Timer can be set up as a 16-bit free-running timer to synchronize the receiver
and transmitter timers and provide a timestamp with which to compare the timestamps stored in
GPT3.
16.2.2
Internal MII Operation
For the MII management interface to function properly, the MDIO signal must be connected through
a 10k Ω pull-up resistor to the +3.3 V supply. Failure to connect this pull-up resistor prevents
management transactions on this internal MII to function. Note that it is possible for data transmission
across the MII to still function since the PHY layer auto-negotiates the link parameters by default.
For the MII management interface to function properly, the internal clock must be divided down from
the system clock to a frequency no greater than 2.5 MHz. The Ethernet MAC Management Divider
(MACMDV) register contains the divider used for scaling down the system clock. See page 456 for
more details about the use of this register.
16.2.3
PHY Operation
The Physical Layer (PHY) in the Ethernet Controller includes integrated ENDECs,
scrambler/descrambler, dual-speed clock recovery, and full-featured auto-negotiation functions.
The transmitter includes an on-chip pulse shaper and a low-power line driver. The receiver has an
adaptive equalizer and a baseline restoration circuit required for accurate clock and data recovery.
The transceiver interfaces to Category-5 unshielded twisted pair (Cat-5 UTP) cabling for 100BASE-TX
applications, and Category-3 unshielded twisted pair (Cat-3 UTP) for 10BASE-T applications. The
Ethernet Controller is connected to the line media via dual 1:1 isolation transformers. No external
filter is required.
16.2.3.1
Clock Selection
The Ethernet Controller has an on-chip crystal oscillator which can also be driven by an external
oscillator. In this mode of operation, a 25-MHz crystal should be connected between the XTALPPHY
and XTALNPHY pins. Alternatively, an external 25-MHz clock input can be connected to the XTALPPHY
pin. In this mode of operation, a crystal is not required and the XTALNPHY pin must be tied to ground.
16.2.3.2
Auto-Negotiation
The Ethernet Controller supports the auto-negotiation functions of Clause 28 of the IEEE 802.3
standard for 10/100 Mbps operation over copper wiring. This function is controlled via register
settings. The auto-negotiation function is turned on by default, and the ANEGEN bit in the Ethernet
PHY Management Register 0 - Control (MR0) is set after reset. Software can disable the
auto-negotiation function by clearing the ANEGEN bit. The contents of the Ethernet PHY Management
Register - Auto-Negotiation Advertisement (MR4) are reflected to the Ethernet Controller’s link
partner during auto-negotiation via fast-link pulse coding.
April 05, 2010
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