LM3S6753 Datasheet, PDF (564/625 Pages) Texas Instruments – Stellaris LM3S6753 Microcontroller

Signal Tables
Table 21-5. Signals by Pin Number (continued)
Pin Number
Pin Name
Pin Type Buffer Type^a Description
G12
VDD33
-
Power Positive supply for I/O and some logic.
H1
PD3
I/O
TTL
GPIO port D bit 3.
U1Tx
O
TTL
UART module 1 transmit. When in IrDA mode, this signal has IrDA
modulation.
H2
PD2
I/O
TTL
GPIO port D bit 2.
U1Rx
I
TTL
UART module 1 receive. When in IrDA mode, this signal has IrDA
modulation.
H3
GND
-
Power Ground reference for logic and I/O pins.
H10
VDD33
-
Power Positive supply for I/O and some logic.
H11
RST
I
TTL
System reset input.
H12
PF1
I/O
TTL
GPIO port F bit 1.
J1
XTALNPHY
O
TTL
Ethernet PHY XTALN 25-MHz oscillator crystal output. Leave
unconnected when using a single-ended 25-MHz clock input
connected to the XTALPPHY pin.
J2
XTALPPHY
I
TTL
Ethernet PHY XTALP 25-MHz oscillator crystal input or external
clock reference input.
J3
GND
-
Power Ground reference for logic and I/O pins.
J10
GND
-
Power Ground reference for logic and I/O pins.
J11
PF2
I/O
TTL
GPIO port F bit 2.
LED1
O
TTL
Ethernet LED 1.
J12
PF3
I/O
TTL
GPIO port F bit 3.
LED0
O
TTL
Ethernet LED 0.
K1
PG0
I/O
TTL
GPIO port G bit 0.
K2
PG1
I/O
TTL
GPIO port G bit 1.
K3
ERBIAS
I
Analog 12.4-kΩ resistor (1% precision) used internally for Ethernet PHY.
K4
GNDPHY
-
Power GND of the Ethernet PHY.
K5
GND
-
Power Ground reference for logic and I/O pins.
K6
GND
-
Power Ground reference for logic and I/O pins.
K7
VDD33
-
Power Positive supply for I/O and some logic.
K8
VDD33
-
Power Positive supply for I/O and some logic.
K9
VDD33
-
Power Positive supply for I/O and some logic.
K10
GND
-
Power Ground reference for logic and I/O pins.
K11
XOSC0
I
Analog Hibernation module oscillator crystal input or an external clock
reference input. Note that this is either a 4.194304-MHz crystal or
a 32.768-kHz oscillator for the Hibernation module RTC. See the
CLKSEL bit in the HIBCTL register.
K12
XOSC1
O
Analog Hibernation module oscillator crystal output. Leave unconnected
when using a single-ended clock source.
L1
PC4
I/O
TTL
GPIO port C bit 4.
PhA0
I
TTL
QEI module 0 phase A.
L2
PC7
I/O
TTL
GPIO port C bit 7.
PhB0
I
TTL
QEI module 0 phase B.
564
April 05, 2010
Texas Instruments-Production Data