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LM3S6753 Datasheet, PDF (565/625 Pages) Texas Instruments – Stellaris LM3S6753 Microcontroller
Stellaris® LM3S6753 Microcontroller
Table 21-5. Signals by Pin Number (continued)
Pin Number
Pin Name
Pin Type Buffer Typea Description
L3
PA0
I/O
TTL
GPIO port A bit 0.
U0Rx
I
TTL
UART module 0 receive. When in IrDA mode, this signal has IrDA
modulation.
L4
PA3
I/O
TTL
GPIO port A bit 3.
SSI0Fss
I/O
TTL
SSI module 0 frame.
L5
PA4
I/O
TTL
GPIO port A bit 4.
SSI0Rx
I
TTL
SSI module 0 receive.
L6
PA6
I/O
TTL
GPIO port A bit 6.
CCP1
I/O
TTL
Capture/Compare/PWM 1.
L7
RXIN
I
Analog RXIN of the Ethernet PHY.
L8
TXON
O
Analog TXON of the Ethernet PHY.
L9
MDIO
I/O
TTL
MDIO of the Ethernet PHY.
L10
GND
-
Power Ground reference for logic and I/O pins.
L11
OSC0
I
Analog Main oscillator crystal input or an external clock reference input.
L12
VBAT
-
Power Power source for the Hibernation module. It is normally connected
to the positive terminal of a battery and serves as the battery
backup/Hibernation module power-source supply.
M1
PC5
I/O
TTL
GPIO port C bit 5.
C1+
I
Analog Analog comparator 1 positive input.
M2
PC6
I/O
TTL
GPIO port C bit 6.
CCP3
I/O
TTL
Capture/Compare/PWM 3.
M3
PA1
I/O
TTL
GPIO port A bit 1.
U0Tx
O
TTL
UART module 0 transmit. When in IrDA mode, this signal has IrDA
modulation.
M4
PA2
I/O
TTL
GPIO port A bit 2.
SSI0Clk
I/O
TTL
SSI module 0 clock.
M5
PA5
I/O
TTL
GPIO port A bit 5.
SSI0Tx
O
TTL
SSI module 0 transmit.
M6
NC
-
-
No connect. Leave the pin electrically unconnected/isolated.
M7
RXIP
I
Analog RXIP of the Ethernet PHY.
M8
TXOP
O
Analog TXOP of the Ethernet PHY.
M9
PF0
I/O
TTL
GPIO port F bit 0.
PWM0
O
TTL
PWM 0. This signal is controlled by PWM Generator 0.
M10
WAKE
I
TTL
An external input that brings the processor out of Hibernate mode
when asserted.
M11
OSC1
O
Analog Main oscillator crystal output. Leave unconnected when using a
single-ended clock source.
M12
HIB
O
OD
An open-drain output with internal pull-up that indicates the
processor is in Hibernate mode.
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
Table 21-6. Signals by Signal Name
Pin Name
ADC0
Pin Number
B1
Pin Type
I
Buffer Typea Description
Analog Analog-to-digital converter input 0.
April 05, 2010
565
Texas Instruments-Production Data