LM3S6753 Datasheet, PDF (435/625 Pages) Texas Instruments – Stellaris LM3S6753 Microcontroller

Stellaris® LM3S6753 Microcontroller
Ethernet MAC Raw Interrupt Status(MACRIS) register when the frame received is too large
to fit into the Ethernet Controller’s 2K RAM.
■ Frame Check Sequence (FCS)
The frame check sequence carries the cyclic redundancy check (CRC) value. The CRC is
computed over the destination address, source address, length/type, and data (including pad)
fields using the CRC-32 algorithm. The Ethernet Controller computes the FCS value one nibble
at a time. For transmitted frames, this field is automatically inserted by the MAC layer, unless
disabled by clearing the CRC bit in the MACTCTL register. For received frames, this field is
automatically checked. If the FCS does not pass, the frame is not placed in the RX FIFO, unless
the FCS check is disabled by clearing the BADCRC bit in the MACRCTL register.
16.2.1.2
MAC Layer FIFOs
The Ethernet Controller is capable of simultaneous transmission and reception. This feature is
enabled by setting the DUPLEX bit in the MACTCTL register.
For Ethernet frame transmission, a 2 KB transmit FIFO is provided that can be used to store a single
frame. While the IEEE 802.3 specification limits the size of an Ethernet frame's payload section to
1500 Bytes, the Ethernet Controller places no such limit. The full buffer can be used, for a payload
of up to 2032 bytes (as the first 16 bytes in the FIFO are reserved for destination address, source
address and length/type information).
For Ethernet frame reception, a 2-KB receive FIFO is provided that can be used to store multiple
frames, up to a maximum of 31 frames. If a frame is received, and there is insufficient space in the
RX FIFO, an overflow error is indicated using the FOV bit in the MACRIS register.
For details regarding the TX and RX FIFO layout, refer to Table 16-1 on page 435. Please note the
following difference between TX and RX FIFO layout. For the TX FIFO, the Data Length field in the
first FIFO word refers to the Ethernet frame data payload, as shown in the 5th to nth FIFO positions.
For the RX FIFO, the Frame Length field is the total length of the received Ethernet frame, including
the Length/Type bytes and the FCS bits.
If FCS generation is disabled by clearing the CRC bit in the MACTCTL register, the last word in the
TX FIFO must contain the FCS bytes for the frame that has been written to the FIFO.
Also note that if the length of the data payload section is not a multiple of 4, the FCS field is not be
aligned on a word boundary in the FIFO. However, for the RX FIFO the beginning of the next frame
is always on a word boundary.
Table 16-1. TX & RX FIFO Organization
FIFO Word Read/Write
Sequence
1st
Word Bit Fields
7:0
15:8
23:16
31:24
2nd
7:0
15:8
23:16
31:24
TX FIFO (Write)
RX FIFO (Read)
Data Length Least Significant Frame Length Least
Byte
Significant Byte
Data Length Most Significant Frame Length Most Significant
Byte
Byte
DA oct 1
DA oct 2
DA oct 3
DA oct 4
DA oct 5
DA oct 6
April 05, 2010
435
Texas Instruments-Production Data