LM3S6753 Datasheet, PDF (17/625 Pages) Texas Instruments – Stellaris LM3S6753 Microcontroller

Stellaris® LM3S6753 Microcontroller
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Register 27:
ADC Underflow Status (ADCUSTAT), offset 0x018 ........................................................... 300
ADC Sample Sequencer Priority (ADCSSPRI), offset 0x020 ............................................. 301
ADC Processor Sample Sequence Initiate (ADCPSSI), offset 0x028 ................................. 303
ADC Sample Averaging Control (ADCSAC), offset 0x030 ................................................. 304
ADC Sample Sequence Input Multiplexer Select 0 (ADCSSMUX0), offset 0x040 ............... 305
ADC Sample Sequence Control 0 (ADCSSCTL0), offset 0x044 ........................................ 307
ADC Sample Sequence Result FIFO 0 (ADCSSFIFO0), offset 0x048 ................................ 310
ADC Sample Sequence Result FIFO 1 (ADCSSFIFO1), offset 0x068 ................................ 310
ADC Sample Sequence Result FIFO 2 (ADCSSFIFO2), offset 0x088 ................................ 310
ADC Sample Sequence Result FIFO 3 (ADCSSFIFO3), offset 0x0A8 ............................... 310
ADC Sample Sequence FIFO 0 Status (ADCSSFSTAT0), offset 0x04C ............................. 311
ADC Sample Sequence FIFO 1 Status (ADCSSFSTAT1), offset 0x06C ............................. 311
ADC Sample Sequence FIFO 2 Status (ADCSSFSTAT2), offset 0x08C ............................ 311
ADC Sample Sequence FIFO 3 Status (ADCSSFSTAT3), offset 0x0AC ............................ 311
ADC Sample Sequence Input Multiplexer Select 1 (ADCSSMUX1), offset 0x060 ............... 312
ADC Sample Sequence Input Multiplexer Select 2 (ADCSSMUX2), offset 0x080 ............... 312
ADC Sample Sequence Control 1 (ADCSSCTL1), offset 0x064 ........................................ 313
ADC Sample Sequence Control 2 (ADCSSCTL2), offset 0x084 ........................................ 313
ADC Sample Sequence Input Multiplexer Select 3 (ADCSSMUX3), offset 0x0A0 ............... 315
ADC Sample Sequence Control 3 (ADCSSCTL3), offset 0x0A4 ........................................ 316
ADC Test Mode Loopback (ADCTMLB), offset 0x100 ....................................................... 317
Universal Asynchronous Receivers/Transmitters (UARTs) ..................................................... 318
Register 1: UART Data (UARTDR), offset 0x000 ............................................................................... 326
Register 2: UART Receive Status/Error Clear (UARTRSR/UARTECR), offset 0x004 ........................... 328
Register 3: UART Flag (UARTFR), offset 0x018 ................................................................................ 330
Register 4: UART IrDA Low-Power Register (UARTILPR), offset 0x020 ............................................. 332
Register 5: UART Integer Baud-Rate Divisor (UARTIBRD), offset 0x024 ............................................ 333
Register 6: UART Fractional Baud-Rate Divisor (UARTFBRD), offset 0x028 ....................................... 334
Register 7: UART Line Control (UARTLCRH), offset 0x02C ............................................................... 335
Register 8: UART Control (UARTCTL), offset 0x030 ......................................................................... 337
Register 9: UART Interrupt FIFO Level Select (UARTIFLS), offset 0x034 ........................................... 339
Register 10: UART Interrupt Mask (UARTIM), offset 0x038 ................................................................. 341
Register 11: UART Raw Interrupt Status (UARTRIS), offset 0x03C ...................................................... 343
Register 12: UART Masked Interrupt Status (UARTMIS), offset 0x040 ................................................. 344
Register 13: UART Interrupt Clear (UARTICR), offset 0x044 ............................................................... 345
Register 14: UART Peripheral Identification 4 (UARTPeriphID4), offset 0xFD0 ..................................... 347
Register 15: UART Peripheral Identification 5 (UARTPeriphID5), offset 0xFD4 ..................................... 348
Register 16: UART Peripheral Identification 6 (UARTPeriphID6), offset 0xFD8 ..................................... 349
Register 17: UART Peripheral Identification 7 (UARTPeriphID7), offset 0xFDC ..................................... 350
Register 18: UART Peripheral Identification 0 (UARTPeriphID0), offset 0xFE0 ...................................... 351
Register 19: UART Peripheral Identification 1 (UARTPeriphID1), offset 0xFE4 ...................................... 352
Register 20: UART Peripheral Identification 2 (UARTPeriphID2), offset 0xFE8 ...................................... 353
Register 21: UART Peripheral Identification 3 (UARTPeriphID3), offset 0xFEC ..................................... 354
Register 22: UART PrimeCell Identification 0 (UARTPCellID0), offset 0xFF0 ........................................ 355
Register 23: UART PrimeCell Identification 1 (UARTPCellID1), offset 0xFF4 ........................................ 356
Register 24: UART PrimeCell Identification 2 (UARTPCellID2), offset 0xFF8 ........................................ 357
Register 25: UART PrimeCell Identification 3 (UARTPCellID3), offset 0xFFC ........................................ 358
April 05, 2010
17
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