LM3S6753 Datasheet, PDF (562/625 Pages) Texas Instruments – Stellaris LM3S6753 Microcontroller

Signal Tables
Table 21-5. Signals by Pin Number (continued)
Pin Number
Pin Name
Pin Type Buffer Type^a Description
A10
PC3
I/O
TTL
GPIO port C bit 3.
SWO
O
TTL
JTAG TDO and SWO.
TDO
O
TTL
JTAG TDO and SWO.
A11
PE0
I/O
TTL
GPIO port E bit 0.
PWM4
O
TTL
PWM 4. This signal is controlled by PWM Generator 2.
A12
PE3
I/O
TTL
GPIO port E bit 3.
B1
ADC0
I
Analog Analog-to-digital converter input 0.
B2
ADC3
I
Analog Analog-to-digital converter input 3.
B3
ADC2
I
Analog Analog-to-digital converter input 2.
B4
NC
-
-
No connect. Leave the pin electrically unconnected/isolated.
B5
GNDA
-
Power The ground reference for the analog circuits (ADC, Analog
Comparators, etc.). These are separated from GND to minimize
the electrical noise contained on VDD from affecting the analog
functions.
B6
GND
-
Power Ground reference for logic and I/O pins.
B7
PB5
I/O
TTL
GPIO port B bit 5.
C1-
I
Analog Analog comparator 1 negative input.
B8
PC2
I/O
TTL
GPIO port C bit 2.
TDI
I
TTL
JTAG TDI.
B9
PC1
I/O
TTL
GPIO port C bit 1.
SWDIO
I/O
TTL
JTAG TMS and SWDIO.
TMS
I/O
TTL
JTAG TMS and SWDIO.
B10
CMOD1
I
TTL
CPU Mode bit 1. Input must be set to logic 0 (grounded); other
encodings reserved.
B11
PE2
I/O
TTL
GPIO port E bit 2.
B12
PE1
I/O
TTL
GPIO port E bit 1.
PWM5
O
TTL
PWM 5. This signal is controlled by PWM Generator 2.
C1
NC
-
-
No connect. Leave the pin electrically unconnected/isolated.
C2
NC
-
-
No connect. Leave the pin electrically unconnected/isolated.
C3
VDD25
-
Power Positive supply for most of the logic function, including the
processor core and most peripherals.
C4
GND
-
Power Ground reference for logic and I/O pins.
C5
GND
-
Power Ground reference for logic and I/O pins.
C6
VDDA
-
Power The positive supply (3.3 V) for the analog circuits (ADC, Analog
Comparators, etc.). These are separated from VDD to minimize
the electrical noise contained on VDD from affecting the analog
functions. VDDA pins must be connected to 3.3 V, regardless of
system implementation.
C7
VDDA
-
Power The positive supply (3.3 V) for the analog circuits (ADC, Analog
Comparators, etc.). These are separated from VDD to minimize
the electrical noise contained on VDD from affecting the analog
functions. VDDA pins must be connected to 3.3 V, regardless of
system implementation.
C8
GNDPHY
-
Power GND of the Ethernet PHY.
C9
GNDPHY
-
Power GND of the Ethernet PHY.
562
April 05, 2010
Texas Instruments-Production Data