LM3S6753 Datasheet, PDF (554/625 Pages) Texas Instruments – Stellaris LM3S6753 Microcontroller

Signal Tables
Table 21-2. Signals by Signal Name (continued)
Pin Name
Pin Number Pin Type Buffer Type^a Description
GND
9
-
Power Ground reference for logic and I/O pins.
15
21
33
39
45
54
57
63
69
82
87
94
GNDA
4
-
Power The ground reference for the analog circuits (ADC, Analog
97
Comparators, etc.). These are separated from GND to
minimize the electrical noise contained on VDD from affecting
the analog functions.
GNDPHY
42
-
Power GND of the Ethernet PHY.
85
86
HIB
I2C0SCL
I2C0SDA
51
O
OD
An open-drain output with internal pull-up that indicates the
processor is in Hibernate mode.
70
I/O
OD
I²C module 0 clock.
71
I/O
OD
I²C module 0 data.
IDX0
10
I
TTL
QEI module 0 index.
LDO
7
-
Power Low drop-out regulator output voltage. This pin requires an
external capacitor between the pin and GND of 1 µF or
greater. When the on-chip LDO is used to provide power to
the logic, the LDO pin must also be connected to the VDD25
pins at the board level in addition to the decoupling
capacitor(s).
LED0
59
O
TTL
Ethernet LED 0.
LED1
60
O
TTL
Ethernet LED 1.
MDIO
58
I/O
TTL
MDIO of the Ethernet PHY.
NC
35
-
-
No connect. Leave the pin electrically unconnected/isolated.
OSC0
48
I
Analog Main oscillator crystal input or an external clock reference
input.
OSC1
49
O
Analog Main oscillator crystal output. Leave unconnected when using
a single-ended clock source.
PA0
26
I/O
TTL
GPIO port A bit 0.
PA1
27
I/O
TTL
GPIO port A bit 1.
PA2
28
I/O
TTL
GPIO port A bit 2.
PA3
29
I/O
TTL
GPIO port A bit 3.
PA4
30
I/O
TTL
GPIO port A bit 4.
PA5
31
I/O
TTL
GPIO port A bit 5.
PA6
34
I/O
TTL
GPIO port A bit 6.
PB0
66
I/O
TTL
GPIO port B bit 0.
PB1
67
I/O
TTL
GPIO port B bit 1.
PB2
70
I/O
TTL
GPIO port B bit 2.
554
April 05, 2010
Texas Instruments-Production Data