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DRV8308_15 Datasheet, PDF (50/60 Pages) Texas Instruments – DRV8308 Brushless DC Motor Controller
DRV8308
SLVSCF7A – FEBRUARY 2014 – REVISED OCTOBER 2014
www.ti.com
9.3 Do's and Don'ts
9.3.1 RESET and ENABLE Considerations
Since the ENABLE function doubles as a sleep (low-power shutdown) function, there are some important
considerations when asserting and deasserting ENABLE and RESET.
While the motor driver is enabled, the deassertion of ENABLE initiates a stop-and-power-down sequence. This
sequence starts by disabling the motor (either braking or coasting depending on the BRKMOD bit), and waiting
for rotation to stop. After rotation is stopped for 1 s (as determined by the absence of transitions on FGOUT), the
internal circuitry is powered-down, the V5 regulator and power switch are disabled, and internal clocks are
stopped.
In this low-power sleep state, the serial interface may still be used to read or write registers. All other logic is
disabled.
After this stop-and-power-down sequence has been initiated (by deasserting the ENABLE terminal for at least
1.2 µs, or by changing the state of the ENPOL bit), the sequence continues to completion, regardless of the state
of ENABLE. If ENABLE is immediately returned to the active state, the motor slows and stops for 1 s, at which
point it starts again.
If RESET is asserted during power-down (at any time after the deassertion of ENABLE is recognized), it is acted
upon when ENABLE is again asserted, and the part powers-up.
If RESET is asserted when ENABLE is active, the motor is stopped similar to the sequence when ENABLE is
deasserted. After it is stopped for 1 s, all internal registers are reloaded with the value contained in OTP memory,
faults are cleared, and internal states (that is, the speed loop datapath) are initialized. The motor remains
disabled until RESET is deasserted.
RESET and ENABLE may be connected together (if the ENPOL bit in OTP memory is programmed so that
ENABLE is active low). When both signals are low, the motor is enabled; when both signals are high, the motor
is disabled. As soon as the signals are returned to high, all registers are reloaded from OTP memory, faults are
cleared, and the motor starts.
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