DRV8308_15 Datasheet, PDF (25/60 Pages) Texas Instruments – DRV8308 Brushless DC Motor Controller

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DRV8308
SLVSCF7A – FEBRUARY 2014 – REVISED OCTOBER 2014
When the motor is braking, all low-side drivers are held in an on state, causing all low-side FETs to turn on, and
the integrator is reset to 0.
In addition, braking can be entered when the ENABLE terminal is made inactive. BRKMOD controls the behavior
of the outputs when ENABLE is inactive. If BRKMOD= 0, the outputs are 3-stated, resulting in the motor
coasting; if BRKMOD = 1, all low-side FETs are turned on, causing the motor to brake.
Table 5. BRKMOD
RESET = 1
BRAKE = active
ENABLE = inactive
DIR
Clock off
Power down
BRKMOD = 0
COAST
Coast
Brake
Coast
Coast
Brake
Coast
BRKMOD = 1
BRAKE
Brake
Brake
Brake
Brake
Brake
Brake
8.3.8 Output Pre-Drivers
The output drivers for each phase consist of N-channel and P-channel MOSFET devices arranged as a CMOS
buffer. They are designed to directly drive the gate of external N-channel power MOSFETs.
The outputs can provide synchronous or asynchronous rectification. In asynchronous rectification, only the high-
side FET is turned on and off with the PWM signal; current is recirculated using external diodes, or the body
diodes of the external FETs. In synchronous rectification, the low side FET is turned on when the high side is
turned off.
Synchronous rectification is enabled or disabled using the SYNRECT control bit. When set to 1, synchronous
rectification is used. In general, synchronous rectification results in better speed control and higher efficiency.
The high-side gate drive output UHSG is driven to VCP whenever the duty cycle output U_PD from the PWM
generator is high, the enable signal U_HS from the commutation logic is active, and the current limit (V_LIMITER) is
not active. If the high-side FET is on and a current limit event occurs, the high-side FET is immediately turned off
until the next PWM cycle.
The low-side gate drive ULSG is driven to VM whenever the internal signal U_LS is high, or whenever
synchronous rectification is active and UHSG is low.
Phases V and W operate in an identical fashion.
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