DRV8308_15 Datasheet, PDF (39/60 Pages) Texas Instruments – DRV8308 Brushless DC Motor Controller

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DRV8308
SLVSCF7A – FEBRUARY 2014 – REVISED OCTOBER 2014
Register Map (continued)
Table 7. Register Descriptions (continued)
ADDRESS
0x04
0x05
0x06
0x07
BIT
15:14
13:12
11
10
9
8
7:6
5:3
2:0
15
14:12
11:0
15
14:13
12
11:0
15:12
11:0
NAME
DESCRIPTION
Locked rotor timeout
LRTIME
00 = RLOCK occurs after 1 s
01 = RLOCK occurs after 3 s
10 = RLOCK occurs after 5 s
11 = RLOCK occurs after 10 s
Sets the frequency to reset the Hall commutation counter
HALLRST
00 = Every Hall_U cycle
01 = Every 2^nd Hall_U cycle
10 = Every 4^th Hall_U cycle
11 = Every 8^th Hall_U cycle
DELAY
Controls whether ADVANCE leads or lags Hall signals
0 = Commutate before Hall signals arrive
1 = Commutate after Hall signals arrive
Enables automatic advance compensation
AUTOADV _{0 = Disabled}
1 = Enabled
Enables automatic gain compensation
AUTOGAIN _{0 = Disabled}
1 = Enabled
ENSINE
Enables 180° sine wave current drive
0 = Disabled
1 = Enabled
Predriver high-current drive time
TDRIVE
00 = 1 µs
01 = 5 µs
10 = 10 µs
11 = 15 µs
Additional dead time added between high-side and low-side driving (typical)
DTIME
000 = 60 ns
001 = 120 ns
010 = 240 ns
011 = 500 ns
100 = 740 ns
101 = 1.0 µs
110 = 1.24 µs
111 = 1.5 µs
Predriver output peak current
IDRIVE
000 = 10 mA
001 = 20 mA
010 = 30 mA
011 = 50 mA
100 = 90 mA
101 = 100 mA
110 = 110 mA
111 = 130 mA
RSVD Reserved
Integrator clock frequency
INTCLK
000 = 50 MHz
001 = 25 MHz
010 = 12.5 MHz
011 = 6.3 MHz
100 = 3.1 MHz
101 = 1.6 MHz
110 = 0.8 MHz
111 = 0.4 MHz
SPDGAIN Speed compensator gain
HALLPOL
Hall polarity
0 = Hall signal logic levels are directly used
1 = Hall signal logic levels are inverted
RSVD Reserved
BYPFILT
Bypass the filter that FILK1 and FILK2 configure
0 = Filter is enabled
1 = Filter is disabled (FILK1 and FILK2 are ignored)
FILK1 Filter coefficient that sets the pole frequency
RSVD Reserved
FILK2 Filter coefficient that sets the zero frequency
TYPE ⁽¹⁾
RW
RW
RW
RW
RW
RW
RW
RW
RW
–
RW
RW
RW
–
RW
RW
–
RW
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