DRV8308_15 Datasheet, PDF (29/60 Pages) Texas Instruments – DRV8308 Brushless DC Motor Controller

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DRV8308
SLVSCF7A – FEBRUARY 2014 – REVISED OCTOBER 2014
8.3.13.3 Motor Overcurrent (OCP)
Overcurrent protection (OCP) is provided on each FET in addition to the current limit circuit. The OCP circuit is
designed to protect the output FETs from atypical conditions such as a short circuit between the motor outputs
and each other, power, or ground.
The OCP circuit is independent from the current limit circuitry. OCP works by monitoring the voltage drop across
the external FETs when they are enabled. If the voltage across a driven FET exceeds V_FETOCP for more than t_OCP
an OCP event is recognized. V_FETOCP is configurable by register OCPTH and t_OCP is configurable by register
OCPDEG.
In addition to monitoring the voltage across the FETs, an OCP event is triggered if the voltage applied to the
ISEN terminal exceeds the V_SENSEOCP threshold voltage.
In the event of an OCP event, FAULTn is pulled low, and the motor driver is disabled.
After a fixed delay of 5 ms, the FAULTn terminal is driven inactive and the motor driver is re-enabled.
The OCP bit in the FAULT register is set when an OCP event is recognized. This bit remains set until a 0 is
written to the OCP bit.
8.3.13.4 Charge Pump Failure (CPFAIL)
If the voltage generated by the high-side charge pump is too low, the high-side output FETs are not fully turned
on, and excessive heating results. To protect against this, the DRV8308 device has a circuit that monitors the
charge pump voltage.
If the charge pump voltage drops below VCPFAIL, the FAULTn terminal is pulled low and the motor driver is
disabled. After the charge pump voltage returns to a voltage above the VCPFAIL threshold, the FAULTn terminal
is high impedance and operation of the motor driver automatically resumes.
The CPFAIL bit in the FAULT register is set when the charge pump voltage drops below VCPFAIL. This bit
remains set until a 0 is written to the CPFAIL bit.
At power-up, the CPFAIL bit is set.
8.3.13.5 Charge Pump Short (CPSC)
To protect against excessive power dissipation inside the DRV8308 device, a circuit monitors the charge pump
and disables it in the event of a short circuit on the PCB.
If a short circuit is detected on the charge pump, the FAULTn terminal is pulled low and the motor driver is
disabled. After a fixed period of 5 s, the FAULTn terminal is high impedance and operation of the motor driver
automatically resumes. If the short circuit condition is still present, the cycle repeats.
The CPSC bit in the FAULT register is set when a short circuit is detected on the charge pump. This bit remains
set until a 0 is written to the CPSC bit.
8.3.13.6 Rotor Lockup (RLOCK)
Circuitry in the DRV8308 device detects a locked or stalled rotor. This can occur in the event of a mechanical
jam or excessive load torque that causes the motor to stop rotating while enabled. The rotor lock condition is set
if there are no transitions detected on the FGOUT signal for a programmable period of time (set by the LRTIME
register bits). RLOCK will also occur if the 3 Hall signals are an invalid state (all High or all Low), which can be
caused by a bad wire connection. RLOCK also occurs in Clock PWM Mode if BRAKE is asserted while the clock
stays running.
If a locked rotor condition is recognized, the FAULTn terminal is pulled low, the motor driver is disabled and the
RLOCK bit in the FAULT register is set. The RLOCK bit remains set until a 0 is written to the RLOCK bit.
If the RETRY bit is set, the part re-enables itself after a fixed delay of 5 s.
If the RETRY bit is not set, the part disables the pre-drivers until RESET is asserted, or power has been
removed and reapplied to the device.
Copyright © 2014, Texas Instruments Incorporated
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