DRV8308_15 Datasheet, PDF (31/60 Pages) Texas Instruments – DRV8308 Brushless DC Motor Controller

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DRV8308
SLVSCF7A – FEBRUARY 2014 – REVISED OCTOBER 2014
8.4 Device Functional Modes
8.4.1 Modes of Speed Input
The DRV8308 device is designed to support a wide range of motor speeds and constructions. Speeds of up to
approximately 50000 RPM are supported with motor constructions of up to 16 poles, or corresponding lower
speeds with more poles. This translates into a Hall sensor speed of up to 6.7 kHz. (The frequency of one Hall
sensor can be calculated by RPM × (motor poles) / 120.)
Speed control of the motor is accomplished by varying the duty cycle applied to the external FETs. Three
methods of speed control input are possible with the DRV8308 device:
• Clock Frequency Mode: This is closed-loop speed control that locks the FGOUT frequency with the CLKIN
frequency.
• Clock PWM Mode: This is open-loop, where the duty cycle of the clock on CLKIN scales the speed of the
motor.
• Internal Register PWM Mode: This is open-loop, where register SPEED divided by 4095 commands the
input duty cycle.
The mode used is set by the SPDMODE register.
8.4.1.1 Clock Frequency Mode
For a practical guide on tuning closed-loop speed control, refer to Section 3 of the DRV8308EVM User's Guide
SLVUA41.
In Clock Frequency Mode, the clock signal is deglitched by the 51.2-MHz clock. The deglitched input, along with
the FG signal (derived from the FG amplifier, TACH input, or the Hall sensors), are input to a speed differentiator,
where the CLKIN signal is compared to the actual speed of the motor (determined by the FG frequency). The
speed differentiator outputs are UP and DOWN pulses.
The deglitcher and speed differentiator are shown in Figure 17:
Sync and Deglitch
Speed Compare
CLKIN/PWMIN
CLK50
Deglitch
Signal must be high or low
for two consecutive CLK50
edges for the deglitched
output to change
CLK_DEG
FG
REF
UP
Speed
Diff.
IN
DOWN
PWM_DEG
Figure 17. Deglitcher and Speed Differentiator
The UP and DOWN outputs of the speed differentiator are integrated by accumulating the value set by the
SPDGAIN register for each cycle of the integrator clock (CLK50 divided by the value of the INTCLK register) that
an UP or DOWN signal is active. If UP is active, the amount is added to the current integrator output; if the
DOWN input is active, the value is subtracted. If neither signal is active, the integrator output remains the same.
Note that the integrator output is reset to 0 at any time the motor is disabled or in brake, and at reset. The
integrator output does not roll over at maximum or minimum count.
At the moment that ENABLE is made active, the integrator and filters are reset to 0. If there are no transitions on
the CLKIN terminal, no UP pulses are generated, so the integrator remains at 0, and the motor is not driven.
Once the motor is running, if the signal on CLKIN stops, DOWN pulses are generated until the integrator reaches
0. This actively decelerates the motor (brake) until the motor stops.
Copyright © 2014, Texas Instruments Incorporated
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