DRV8308_15 Datasheet, PDF (23/60 Pages) Texas Instruments – DRV8308 Brushless DC Motor Controller

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DRV8308
SLVSCF7A – FEBRUARY 2014 – REVISED OCTOBER 2014
8.3.5 Commutation Logic Block Diagram
A block diagram of the commutation logic is shown in Figure 12.
DELAY
Commutation Timer
0
CLK50
DQ
LD
25b CNT
CLK50
DQ
LD
25b REG
ADVANCE
!
HALL_PERIOD
/960
D
LD ^{Q = 0}
CLK50
17b DN CNT
Auto
Advance
Cnt = 0
D
Q ^COMCNT
LD
DIR_PWM
BKRMOD
0 - 960 count
ENSINE
Phase
Advance /
Commutation
Counter
ENABLE
DIR
HU_SYN
HV_SYN
HW_SYN
Commutation
Tables
U_MOD
V_MOD
W_MOD
U_LS
V_LS
W_LS
HALL_U
CLK50
HALL_V
HALL_W
Sync HU_SYN
Deglitch
Sync HV_SYN _CLK50
Deglitch
DQ
Sync HW_SYN
Deglitch
ENABLE
ENABLE = 0
Clears all
Registers and
Counters
HALLRST
/N
(1,2,4,8)
Speed Change Detect
DQ
Diff.
A
A>B
B
/4,/8, .../512
SPDTH
MINSPD
A
A>B
B
Minimum Speed
Detect
DIRPWM
INTSAT
BASIC
SPDREVS
8b DN CNT
LD Q
D
Minimum Revs at
Speed
Lock Detect Logic
Figure 12. Commutation Logic
ENL_180
8.3.6 Commutation Parameters
A number of commutation parameters are programmable through registers accessed through the serial interface,
including:
• ADVANCE — The phase of commutation is advanced (or delayed) relative to the Hall sensor transition by this
8-bit amount. Units are in commutation clocks, which is 1 / 960 of the HALL_U period. Note that phase
advance is only applicable in single-Hall commutation modes. An automatic phase advance compensation
mode can also be enabled by the AUTOADV bit (see Auto Gain and Advance Compensation for details).
Space
• DELAY — if set, commutation is delayed relative to Hall transitions; if cleared, commutation is advanced
relative to Hall transitions.
Space
• BASIC — If set, commutation is a basic 120° 3-Hall mode with no ADVANCE.
Space
• ENSINE — The ENSINE bit, when set, selects 180° sinusoidal commutation. The BASIC bit must also be 0.
Space
• HALLRST — HALLRST sets how many HALL_U cycles pass for each commutation counter reset. In other
words, the commutation counter is reset every N HALL_U edges. Selections available are 1, 2, 4, and 8.
Space
• MINSPD — Sets the minimum Hall_U period that LOCK can be set. The 8-bit field represents 2.56 ms/count,
with a max value of 652.8 ms.
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