DRV8308_15 Datasheet, PDF (36/60 Pages) Texas Instruments – DRV8308 Brushless DC Motor Controller

DRV8308
SLVSCF7A – FEBRUARY 2014 – REVISED OCTOBER 2014
www.ti.com
Device Functional Modes (continued)
To program the EEPROM device in-circuit while connected to the DRV8308 device, place the DRV8308 device
into the reset state by driving RESET high. This 3-states the serial interface terminals and allows them to be
overdriven by external programming logic. Alternatively, the EEPROM may be programmed off-board before
assembly. The DRV8308 device cannot program an EEPROM.
8.5 Programming
8.5.1 Serial Interface
A simple SPI serial interface is used to write to the control registers in the DRV8308 device. Optionally, the
interface can be configured to automatically load the registers from an external EEPROM device.
Data is shifted into a holding register when SCS is active high. When SCS is returned to inactive (low), the data
received is latched into the addressed register.
8.5.2 Serial Data Format
The serial data consists of a 24-bit serial write, with a read or write bit, 7 address bits, and 16 data bits. The
address bits identify one of the registers defined in Table 7.
To write to a register, data is shifted in after the address as shown in Figure 23:
SCS
SCLK
SDATI
1
2
3
4
5
6
7
8 Note 1 9
10
11
12
13
14
15
16 Note 1 17
18
19
20
21
22
23
24
WRT A6
A5
A4
A3
A2
A1
A0
X
D15 D14 D13 D12 D11 D10 D9
D8
X
D7 D6
D5
D4 D3
D2
D1
D0
Note 2
A. Any amount of time may pass between bits, as long as SCS stays active high. This allows 8-bit writes to be used.
B. Any additional clock edges encountered after the 24^th edge are ignored.
Figure 23. SDF Timing Diagram 1
Data may be read from the registers through the SDATO terminal. During a read operation, only the address is
used from the SDATI terminal; the data bits following are ignored. Reading is enabled by setting the READ bit at
the beginning of the access:
SCS
SCLK
SDATI
1
2
3
4
5
6
7
8 Note 1 9
10
11
12
13
14
15
16 Note 1 17
18
19
20
21
22
23
24
READ A6
A5
A4
A3
A2
A1
A0
Note 2
SDATO
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
A. Any amount of time may pass between bits, as long as SCS stays active high. This allows 8-bit writes to be used.
B. Any additional clock edges encountered after the 24^th edge are ignored.
Figure 24. SDF Timing Diagram 2
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