DRV8308_15 Datasheet, PDF (16/60 Pages) Texas Instruments – DRV8308 Brushless DC Motor Controller

DRV8308
SLVSCF7A – FEBRUARY 2014 – REVISED OCTOBER 2014
Feature Description (continued)
HALL_U
HALL_V
HALL_W
FGFB
TACH
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FGOUT when FGSEL=0
(HALL_U)
FGOUT when FGSEL=1
(XOR of the Halls)
FGOUT when FGSEL=2
(FG amplifier)
FGOUT when FGSEL=3
(TACH)
Figure 6.
8.3.3 Enable, Reset, and Clock Generation
The ENABLE terminal is used to start and stop motor operation. ENABLE can be programmed to be active high
or active low, depending on the state of the ENPOL bit; if ENPOL = 0, ENABLE is active high. If ENPOL = 1, the
ENABLE terminal is active low.
The polarity of ENABLE cannot be modified during operation through register writes; it is controlled only by the
contents of the ENPOL bit in OTP memory.
When ENABLE is active, operation of the motor is enabled. When ENABLE is made inactive, the speed control
loop is reset, and the motor either brakes or coasts depending on the state of the BRKMOD bit. After motor
rotation has stopped (when no transitions occur on the FGOUT terminal for a period of 1 s), the DRV8308 device
enters a low-power standby state. In the standby state, the motor driver circuitry is disabled (all gate drive
outputs are driven low, so the FET outputs are high-impedance), the gate drive regulator and charge pump are
disabled, the VREG regulator and VSW power switch are disabled, and all analog circuitry is placed into a low
power state. The digital circuitry in the device still operates in standby mode.
All internal logic is reset in three different ways:
1. Upon device power-up.
2. When VM drops below V_RESET.
3. When the RESET terminal is high while ENABLE is active.
If RESET is high while ENABLE is inactive, then the registers read as 1. If the RESET terminal is not needed, it
can be connected to GND. The RESET input is deglitched with a 10-µs timer on assertion and deassertion.
An internal clock generator provides all timing for the DRV8308 device. The master oscillator runs at 100 MHz.
This clock is divided to a nominal 50-MHz frequency that clocks the remainder of the digital logic.
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