DRV8308_15 Datasheet, PDF (24/60 Pages) Texas Instruments – DRV8308 Brushless DC Motor Controller

DRV8308
SLVSCF7A – FEBRUARY 2014 – REVISED OCTOBER 2014
www.ti.com
Space
• SPDREVS — After the MINSPD and SPEEDTH criteria are met, SPDREVS adds a minimum number of
Hall_U periods that must occur for LOCK to be set.
Space
• SPEEDTH — Sets how much speed variation is allowed across Hall_U periods while keeping LOCK set. This
3-bit field sets the percentage variation allowed by changing a programmable divider. Divisions of 1/4, 1/8,
1/16, 1/32, 1/64, 1/128, 1/256, and 1/512 are supported. These divisors correspond to 25%, 12.5%, 6.25%,
3.13%, 1.56%, 0.78%, 0.39%, and 0.20% variation per revolution.
Space
• SPEED — In the Internal Register PWM Mode, SPEED divided by 4095 sets the input duty cycle. In Clock
Frequency Mode, SPEED sets the open-loop gain during spin-up before LOCKn goes Low.
The diagram below shows how the lock parameters (MINSPD, SPEEDTH, and SPDREV) affect commutation
mode.
Frequency
HALL_U
SPEEDTH
SPDREVS:
MINSPD and SPEEDTH criteria
meet for the number of electrical
revs before 180 commutation
SPEEDTH:
enable
How much speed variation is allowed
while 180 commutation
MINSPD:
Sets the mim speed that 180°
commutation can be enabled
SPDREVS
ENL_180
H: 180° commutation
L: 120° commutation
Commutation
Table Output
120° Commutation
180° Commutation
120
180
Figure 13. Commutation Parameters
8.3.7 Braking
Motor braking can be initiated by the BRKPOL register bit as well as the BRAKE terminal. The BRKPOL register
bit can also be used to program the polarity of the BRAKE terminal, as it is combined with the terminal with an
exclusive-OR function as follows:
Table 4. Brake Behavior
BRAKE Terminal
0
0
1
1
BRKPOL Register Bit
0
1
0
1
Resulting Function
Not brake
Brake
Brake
Not brake
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