DRV8308_15 Datasheet, PDF (40/60 Pages) Texas Instruments – DRV8308 Brushless DC Motor Controller

DRV8308
SLVSCF7A – FEBRUARY 2014 – REVISED OCTOBER 2014
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Register Map (continued)
ADDRESS
0x08
0x09
0x0A
0x0B
BIT
15:13
12
11:0
15:12
11:0
15:14
13:12
11
10
9:0
15:12
11:0
Table 7. Register Descriptions (continued)
NAME
DESCRIPTION
RSVD Reserved
Bypass the compensator (COMPK1 and COMPK2 are ignored)
BYPCOMP _{0 = Filter is enabled}
1 = Filter is disabled (FILK1 and FILK2 are ignored)
COMPK1 Compensator coefficient that sets the pole frequency
Autoadvance setpoint
AA_SETPT
0000 = 3 Hz
0001 = 6 Hz
0010 = 12 Hz
0011 = 24 Hz
0100 = 48 Hz
0101 = 95 Hz
0110 = 191 Hz
0111 = 382 Hz
1000 = 763 Hz
1001 = 1.5 kHz
1010 = 3 kHz
1011 = 6 kHz
1100 = 12 kHz
1101 = 24 kHz
1110 = 49 kHz
1111 = 98 kHz
COMPK2 Compensator coefficient that sets the zero frequency
OCPDEG
OCPTH
Overcurrent protection deglitch time to ignore voltage spikes. Controls t_OCP and t_BLANK.
00: t_ocp = 1.6µs, t_BLANK = 2µs
01: t_ocp = 2.3µs, t_BLANK = 3µs
10: t_ocp = 3µs, t_BLANK = 3.75µs
11: t_ocp = 5µs, t_BLANK = 6µs
Protection threshold for V_FETOCP
00 = 250 mV
01 = 500 mV
10 = 750 mV
11 = 1000 mV
OVTH
Protection threshold for V_OVLO
0 = 34.5 V
1 = 28 V
Writing this bit over SPI requires ENABLE to be active.
VREG_EN _{0 = VREG is enabled only when ENABLE is active}
1 = VREG is always enabled
LOOPGAIN Sets the overall gain for the speed control loop
RSVD Reserved
SPEED
In the Internal Register PWM Mode, SPEED divided by 4095 sets the input duty cycle. In
Clock Frequency Mode, SPEED sets the open-loop gain during spin-up before LOCKn goes
Low.
TYPE ⁽¹⁾
–
RW
RW
RW
RW
RW
RW
RW
RW
RW
–
RW
40
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