DRV8308_15 Datasheet, PDF (27/60 Pages) Texas Instruments – DRV8308 Brushless DC Motor Controller

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DRV8308
SLVSCF7A – FEBRUARY 2014 – REVISED OCTOBER 2014
The peak drive current of the pre-drivers is adjustable by setting the IDRIVE register bits. Peak drive currents
may be set between 10 and 130 mA. Adjusting the peak current changes the output slew rate, which also
depends on the FET input capacitance and gate charge.
When changing the state of the output, the peak current is applied for a short period of time (t_DRIVE), to charge
the gate capacitance. This time is selected by setting the TDRIVE register bits. Times of 1, 5, 10, or 15 µs may
be selected. After this time, a weak current source is used to keep the gate at the desired state. When selecting
the gate drive strength for a given external FET, the selected current must be high enough to fully charge and
discharge the gate during the time when driven at full current, or excessive power is dissipated in the FET.
During high-side turn-on, the low-side gate is held low with a low impedance. This prevents the gate-source
capacitance of the low-side FET from inducing turn-on. Similarly, during low-side turn-on, the high-side gate is
held off with a low impedance.
The pre-driver circuits include enforcement of a dead time in analog circuitry, which prevents the high-side and
low-side FETs from conducting at the same time. Additional dead time can be added (in digital logic) by setting
the DTIME register bits.
8.3.9 Current Limit
The current limit circuit activates if the voltage detected across the low-side sense resistor exceeds V_LIMITER. This
feature restricts motor current to less than V_LIMITER/R_ISENSE, and it reduces the requirements of the external power
supply. Note that the current limit circuit is ignored immediately after the PWM signal goes active for a short
blanking time, to prevent false trips of the current limit circuit.
If current limit activates, the high-side FET is disabled until the beginning of the next PWM cycle. If synchronous
rectification is enabled when the current limit activates, the low-side FET is activated while the high-side FET is
disabled.
8.3.10 Charge Pump
Since the output stages use N-channel FETs, a gate drive voltage higher than the VM power supply is needed to
fully enhance the high-side FETS. The DRV8308 device integrates a charge pump circuit that generates a
voltage approximately 10 V more than the VM supply for this purpose.
The charge pump requires two external capacitors for operation. For details on these capacitors (value,
connection, and so forth), refer to the Pin Functions table in the Pin Configurations and Functions section.
The charge pump is shutdown when in standby mode (ENABLE inactive).
VM
0.1 µF
35 V
0.1 µF
35 V
VM
CP1
CP2
Charge
Pump
VCP
1 µF
10 V
To Pre-Drivers
Figure 16. Charge Pump
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