DRV8308_15 Datasheet, PDF (28/60 Pages) Texas Instruments – DRV8308 Brushless DC Motor Controller

DRV8308
SLVSCF7A – FEBRUARY 2014 – REVISED OCTOBER 2014
www.ti.com
8.3.11 5-V Linear Regulator
A 5-V linear regulator (VREG) is provided to power internal logic and external circuitry, such as the Hall effect
sensors.
A capacitor must be connected from the VREG output to ground, even if the output is not used for external
circuitry. The recommended capacitor value is a 0.1-μF, 10-V ceramic capacitor.
The VREG output is designed to provide up to 30-mA output current, but power dissipation and thermal
conditions must be considered. As an example, with 24 V in and 20 mA out, power dissipated in the linear
regulator is 19 V × 20 mA = 380 mW.
The VREG regulator is shutdown in standby mode (when ENABLE is inactive).
8.3.12 Power Switch
A low-current switch is provided in the DRV8308 device that can be used to power the Hall sensors or other
external circuitry through the VSW terminal. When ENABLE is active the switch is turned on, connecting the
VSW terminal to VM. When ENABLE is inactive the switch is turned off (standby mode).
8.3.13 Protection Circuits
A number of protection circuits are included in the DRV8308 device. Faults are reported by asserting the
FAULTn terminal (an active-low, open-drain output signal), as well as setting the appropriate bit or bits in the
FAULT register. Note that bits in the FAULT register remain set until either a 0 is written to them, RESET is
asserted, or the device power is cycled.
8.3.13.1 VM Undervoltage Lockout (UVLO)
If the VM power supply drops, there may not be enough voltage to fully turn on the output FETs. Operation in this
condition causes excessive heating in the output FETs. To protect against this, the DRV8308 device contains an
undervoltage lockout circuit.
In the event that the VM supply voltage drops below the undervoltage lockout threshold (V_UVLO), the FAULTn
terminal is driven active and the motor driver is disabled. After VM returns to a voltage above the undervoltage
lockout threshold, the FAULTn terminal is high impedance and operation of the motor driver automatically
resumes.
The UVLO bit in the FAULT register is set. This bit remains set until a 0 is written to the UVLO bit.
At power-up, the UVLO bit is set.
Note that register reads and writes are still possible during the UVLO condition, as long as VM stays above the
VM reset threshold. If VM drops below the VM reset threshold, all registers are reset and register read or write is
not functional.
8.3.13.2 VM Overvoltage (VMOV)
In some cases, if synchronous rectification is used, energy from the mechanical system can be forced back into
the VM power supply. This can result in the VM power supply being boosted by the energy in the mechanical
system, causing breakdown of the output FETs, or damaging the DRV8308 device. To protect against this, the
DRV8308 device has overvoltage protection.
There are two overvoltage thresholds, selectable by the OVTH bit. An overvoltage event is recognized if the VM
voltage exceeds the selected overvoltage threshold (VM_OVLO). Note that for the output FETs to be protected, they
must be rated for a voltage greater than the selected overvoltage threshold.
In the event of an overvoltage, the FAULTn terminal is pulled low. If synchronous rectification is enabled, the
output stage is forced into asynchronous rectification. After VM returns to a voltage below the overvoltage
threshold, the FAULTn terminal is high impedance. If synchronous rectification was enabled prior to the
overvoltage event, after a fixed 60-µs delay, synchronous rectification is re-enabled.
The VMOV bit in the FAULT register is set. This bit remains set until a 0 is written to the VMOV bit.
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