DRV8308_15 Datasheet, PDF (33/60 Pages) Texas Instruments – DRV8308 Brushless DC Motor Controller

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Device Functional Modes (continued)
DRV8308
SLVSCF7A – FEBRUARY 2014 – REVISED OCTOBER 2014
ReInstpeognrasteor
Section 1
Zero
Section 1
Pole
LOOPGN
Section 2
Pole / Zero
FILK2
FILK1
COMPK1,2
0 Hz
Frequency
Figure 18. Open-Loop Response
The integrator operates on the periods of CLKIN and the Feedback as shown in Figure 19:
SPDGAIN
T_CLKIN
T_FB
1  ^TCLKIN
T_FB
1.6 ˜ SPDGAIN
2 ^INTCLK
³
INTCLK
Figure 19. Integrator and Filters
8.4.1.2 Clock PWM and Internal Register PWM Modes
In PWM input modes, the PWM input signal is timed using a 50 MHz clock to generate a 12-bit number that
corresponds to the duty cycle of the incoming PWM signal. The input PWM frequency should be between 16 and
50 kHz, higher PWM frequencies work, but resolution is degraded. Note that the gate driver’s output PWM
frequency is independent of the speed control PWM input frequency; the output PWM frequency is selected by
the PWMF register bits.
The measured input duty cycle is scaled by the contents of the MOD120 register. With a full-scale MOD120
register (4095 decimal), the output duty cycle is 2× the input duty cycle. To make the output duty cycle equal to
the input, a value of 2048 decimal should be written to MOD120.
An additional multiplication factor of 2 is introduced when the BYPCOMP bit is set; if BYPCOMP is set, the
output duty cycle is 4× the input duty cycle (when MOD120 is 4095).
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