LSM303AH Datasheet, PDF (62/82 Pages) –

Register description
LSM303AH
8.23
WAKE_UP_DUR_A (34h)
Wakeup and sleep duration configuration register (r/w)
Table 70. WAKE_UP_DUR_A register
INT1_
FF_DUR5 WU_DUR1 WU_DUR0
FSS7
SLEEP_ SLEEP_
DUR3
DUR2
SLEEP_
DUR1
SLEEP_
DUR0
FF DUR5
Table 71. WAKE_UP_DUR_A register description
Free-fall duration. In conjunction with FF_DUR [4:0] bit in FREE_FALL_A
(35h) register. 1 LSB = 1 TODR
WU_DUR [1:0]
Wakeup duration. 1 LSB = 1 TODR
INT1_FSS7
FF interrupt is routed on INT1 pad
(0: disabled; 1: enabled)
SLEEP_DUR[5:0] Duration to go in sleep mode. 1 LSB = 512 TODR
8.24
FREE_FALL_A (35h)
Free-fall duration and threshold configuration register (r/w)
Table 72. FREE_FALL_A register
FF_DUR4 FF_DUR3 FF_DUR2 FF_DUR1 FF_DUR0 FF_THS2 FF_THS1 FF_THS0
FF_DUR [4:0]
FF_THS [2:0]
Table 73. FREE_FALL_A register description
Free-fall duration. In conjunction with FF_DUR5 bit in WAKE_UP_DUR_A (34h)
register. 1 LSB = 1 TODR.
Free-fall threshold @ FS = 2 g (refer to Table 74)
FF_THS1
0
0
0
0
1
1
1
1
Table 74. FREE_FALL_A threshold decoding @ 2 g FS
FF_THS1
FF_THS0
Threshold decoding (degrees)
0
0
5
0
1
7
1
0
8
1
1
10
0
0
11
0
1
13
1
0
15
1
1
16
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