LSM303AH Datasheet, PDF (56/82 Pages) –

Register description
LSM303AH
8.8
FIFO_CTRL_A (25h)
FIFO control register 5 (r/w).
FMODE2
FMODE1
Table 45. FIFO_CTRL_A register
FMODE0
INT2_STEP_
COUNT_OV
MODULE_
TO_FIFO
0⁽¹⁾
1. This bit must be set to '0' for correct device operation.
0⁽¹⁾
IF_CS_PU_
DIS
Table 46. FIFO_CTRL_A register description
FMODE [2:0] FIFO mode selection bits. Default: 000. For further details refer to Table 47.
INT2_STEP_
COUNT_OV
Step counter overflow interrupt enable on INT2 pad. Default value: 0
(0: disabled; 1: enabled)
MODULE_TO_ When set to '1'-logic, module routine result is send to FIFO instead of X,Y,Z
FIFO
acceleration data
IF_CS_PU_DIS When '1'-logic disconnects pull-up in if_cs pad. Default: 0
When the FIFO has been enabled, data acquired has been stored at the accelerometer
ODR and the trigger signal of FIFO writing is the accelerometer internal data-ready.
FIFO data can be stored in default configuration where inertial data as been stored as X, Y,
Z data or in module configuration:
Default configuration: 256-level inertial data (14-bit stored data for X, Y, Z)
User-selectable: 768 module data (14-bit each module)
Table 47. FIFO mode selection
FMODE2 FMODE1 FMODE0
Mode
0
0
0
Bypass mode: FIFO turned off
0
0
1
FIFO mode: Stops collecting data when FIFO is full.
0
1
0
Reserved
0
1
1
Continuous-to-FIFO: Stream mode until trigger is
deasserted, then FIFO mode
1
0
0
Bypass-to-Continuous: Bypass mode until trigger is
deasserted, then FIFO mode
1
0
1
Reserved
1
1
0
Continuous mode: data If the FIFO is full, the new sample
overwrites the older sample.
1
1
1
Reserved
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