LSM303AH Datasheet, PDF (51/82 Pages) –

LSM303AH
8
Register description
Register description
8.1
Module_8bit_A (0Ch)
Module out value (r). This register is a read-only register.
Table 29. Module_8bit_A register
Module_7 Module_6 Module_5 Module_4 Module_3 Module_2 Module_1 Module_0
Table 30. Module_8bit_A register description
Module [7:0] Module output value (8-bit). Default value: 0
8.2
WHO_AM_I_A (0Fh)
Who_AM_I register (r). This register is a read-only register. Its value is fixed at 43h.
Table 31. WHO_AM_I_A register default values
0
1
0
0
0
0
1
1
8.3
CTRL1_A (20h)
Control register 1 (r/w)
ODR3
ODR2
Table 32. CTRL1_A register
ODR1
ODR0
FS1
FS0
HF_ODR
BDU
ODR [3:0]
FS [1:0]
HF_ODR
BDU
Table 33. CTRL1_A register description
Output data rate & power mode selection. Default value: 0000 (see Table 34)
Full-scale selection. Default value: 00 (00: ±2 g; 01: ±16 g; 10: ±4 g; 11: ±8 g)
High-frequency ODR mode enable. Default value: 0
Block data update. Default value: 0
(0: continuous update; 1: output registers not updated until MSB and LSB read)
ODR [3:0] is used to set the power mode and ODR selection. The following table lists the bit
settings for power-down mode and each available frequency.
Table 34. ODR register setting: power down (PD) and low power (LP)
ODR[3:0]
HF_ODR
ODR selection [Hz] Bit resolution
Mode
0000
-
-
-
PD
1000
-
1
10
LP
1001
-
12.5
10
LP
1010
-
25
10
LP
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