LSM303AH Datasheet, PDF (52/82 Pages) –

Register description
LSM303AH
Table 34. ODR register setting: power down (PD) and low power (LP) (continued)
ODR[3:0]
HF_ODR
ODR selection [Hz] Bit resolution
Mode
1011
-
50
10
LP
1100
-
100
10
LP
1101
-
200
10
LP
1110
-
400
10
LP
1111
-
800
10
LP
Table 35. ODR register setting: high resolution (HR) and high frequencies (HF)
ODR[3:0]
HF_ODR
ODR selection [Hz] Bit resolution
Mode
0001
-
12.5
0010
-
25
0011
-
50
14
HR
14
HR
14
HR
0100
-
100
0101
0
200
14
HR
14
HR
0110
0
400
0111
0
800
14
HR
14
HR
0101
1
0110
1
1600
3200
12
HF
12
HF
0111
1
6400
12
HF
The BDU bit is used to inhibit the update of the output registers until both upper and lower
register parts are read. In default mode (BDU = ‘0’) the output register values are updated
continuously. When the BDU is activated (BDU = ‘1’), the content of the output registers is
not updated until both MSB and LSB are read which avoids reading values related to
different sample times.
8.4
CTRL2_A (21h)
Control register 2 (r/w)
BOOT
SOFT_
RESET
Table 36. CTRL2_A register
0⁽¹⁾
FUNC_
CFG_EN^(2)(3)(4)
FDS_
SLOPE
IF_ADD_
INC
I2C_
DISABLE
SPI_ENABLE
1. This bit must be set to ‘0’ for the correct operation of the device.
2. When this bit is enabled, only advanced configuration registers can be written. For proper functionality of
the device, all the other registers must not be modified.
3. Details of advanced configuration registers are available in Section 9: Advanced configuration register
mapping and Section 10: Advanced configuration registers description.
4. To disable the advanced configuration, bit FUNC_CFG_EN in CTRL2_A (3Fh) must be set to '0'. Refer to
Section 10.4: CTRL2_A (3Fh)
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