M36W832TE Datasheet, PDF (25/64 Pages) STMicroelectronics – 32 Mbit 2Mb x16, Boot Block Flash Memory and 8 Mbit 512Kb x16 SRAM, Multiple Memory Product

M36W832TE, M36W832BE
SRAM Operations
There are five standard operations that control the
SRAM component. These are Bus Read, Bus
Write, Standby/Power-down, Data Retention and
Output Disable. A summary is shown in Table 2,
Main Operation Modes
Read. Read operations are used to output the
contents of the SRAM Array.
The SRAM is in Byte Read mode whenever Write
Enable, WS, is at V_IH, Output Enable, GS, is at V_IL,
Chip Enable, E1S, is at V_IL, Chip Enable, E2S, is
at V_IH, and UBS or LBS is at V_IL.
The SRAM is in Word Read mode whenever Write
Enable, WS, is at V_IH, Output Enable, GS, is at V_IL,
Byte Enable inputs UBS and LBS are both at V_IL
and the two Chip Enable inputs, E1S, and E2S are
Don’t Care.
Valid data will be available on the output pins after
a time of t_AVQV after the last stable address. If the
Chip Enable or Output Enable access times are
not met, data access will be measured from the
limiting parameter (t_E1LQV, t_E2HQV, or t_GLQV) rath-
er than the address. Data out may be indetermi-
nate at t_E1LQX, t_E2HQX and t_GLQX, but data lines
will always be valid at t_AVQV (see Table 20, Figures
14 and 15).
Write. Write operations are used to write data to
the SRAM. The SRAM is in Write mode whenever
WS and E1S are at V_IL, and E2S is at V_IH. Either
the Chip Enable inputs, E1S and E2S, or the Write
Enable input, WS, must be deasserted during ad-
dress transitions for subsequent write cycles.
A Write operation is initiated when E1S is at V_IL,
E2S is at V_IH and WS is at V_IL. The data is latched
o the falling edge of E1S, the rising edge of E2S or
the falling edge of WS, whichever occurs last. The
Write cycle is terminated on the rising edge of
E1S, the rising edge of WS or the falling edge of
E2S, whichever occurs first.
If the Output is enabled (E1S=V_IL, E2S=V_IH and
GS=V_IL), then WS will return the outputs to high
impedance within t_WLQZ of its falling edge. Care
must be taken to avoid bus contention in this type
of operation. The Data input must be valid for t_D-
VWH ^{before the rising edge of Write Enable, for}
t_DVE1H before the rising edge of E1S or for t_DVE2L
before the falling edge of E2S, whichever occurs
first, and remain valid for t_WHDX, t_E1HAX or t_E2LAX
(see Table 21, Figure 17, 18, 19 and 20).
Standby/Power-Down. The SRAM component
has a chip enabled power-down feature which in-
vokes an automatic standby mode (see Table 20
and Figure 16). The SRAM is in Standby mode
whenever either Chip Enable is deasserted, E1S
at V_IH or E2S at V_IL.
Data Retention. The SRAM data retention per-
formance as V_DDS goes down to V_DR are de-
scribed in Table 22, Figures 21 and 22, SRAM
Low V_DDS Data Retention AC Waveforms, E1S
Controlled and SRAM Low V_DDS Data Retention
AC Waveforms, E2S Controlled, respectively.
Output Disable. The data outputs are high im-
pedance when the Output Enable, GS, is at V_IH
with Write Enable, WS, at V_IH.
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