M36W832TE Datasheet, PDF (16/64 Pages) STMicroelectronics – 32 Mbit 2Mb x16, Boot Block Flash Memory and 8 Mbit 512Kb x16 SRAM, Multiple Memory Product

M36W832TE, M36W832BE
s The second latches the block address in the
internal state machine and starts the Program/
Erase Controller.
If the second bus cycle is not Write Erase Confirm
(D0h), Status Register bits b4 and b5 are set and
the command aborts.
Erase aborts if Reset turns to V_IL. As data integrity
cannot be guaranteed when the Erase operation is
aborted, the block must be erased again.
During Erase operations the memory will accept
the Read Status Register command and the Pro-
gram/Erase Suspend command, all other com-
mands will be ignored. Typical Erase times are
given in Table 8, Flash Program, Erase Times and
Program/Erase Endurance Cycles.
See Appendix C, Figure 30, Erase Flowchart and
Pseudo Code, for a suggested flowchart for using
the Erase command.
Program Command. The memory array can be
programmed word-by-word. Two bus write cycles
are required to issue the Program Command.
s The first bus cycle sets up the Program
command.
s The second latches the Address and the Data to
be written and starts the Program/Erase
Controller.
During Program operations the memory will ac-
cept the Read Status Register command and the
Program/Erase Suspend command. Typical Pro-
gram times are given in Table 8, Flash Program,
Erase Times and Program/Erase Endurance Cy-
cles.
Programming aborts if Reset goes to V_IL. As data
integrity cannot be guaranteed when the program
operation is aborted, the block containing the
memory location must be erased and repro-
grammed.
See Appendix C, Figure 26, Program Flowchart
and Pseudo Code, for the flowchart for using the
Program command.
Double Word Program Command. This feature
is offered to improve the programming throughput,
writing a page of two adjacent words in paral-
lel.The two words must differ only for the address
A0. Programming should not be attempted when
V_PPF is not at V_PPH.
Three bus write cycles are necessary to issue the
Double Word Program command.
s The first bus cycle sets up the Double Word
Program Command.
s The second bus cycle latches the Address and
the Data of the first word to be written.
s The third bus cycle latches the Address and the
Data of the second word to be written and starts
the Program/Erase Controller.
Read operations output the Status Register con-
tent after the programming has started. Program-
ming aborts if Reset goes to V_IL. As data integrity
cannot be guaranteed when the program opera-
tion is aborted, the block containing the memory
location must be erased and reprogrammed.
See Appendix C, Figure 27, Double Word Pro-
gram Flowchart and Pseudo Code, for the flow-
chart for using the Double Word Program
command.
Quadruple Word Program Command. This
feature is offered to improve the programming
throughput, writing a page of four adjacent words
in parallel.The four words must differ only for the
addresses A0 and A1. Programming should not be
attempted when V_PPF is not at V_PPH.
Five bus write cycles are necessary to issue the
Quadruple Word Program command.
s The first bus cycle sets up the Quadruple Word
Program Command.
s The second bus cycle latches the Address and
the Data of the first word to be written.
s The third bus cycle latches the Address and the
Data of the second word to be written.
s The fourth bus cycle latches the Address and
the Data of the third word to be written.
s The fifth bus cycle latches the Address and the
Data of the fourth word to be written and starts
the Program/Erase Controller.
Read operations output the Status Register con-
tent after the programming has started. Program-
ming aborts if Reset goes to V_IL. As data integrity
cannot be guaranteed when the program opera-
tion is aborted, the block containing the memory
location must be erased and reprogrammed.
See Appendix C, Figure 28, Quadruple Word Pro-
gram Flowchart and Pseudo Code, for the flow-
chart for using the Quadruple Word Program
command.
Clear Status Register Command. The Clear
Status Register command can be used to reset
bits 1, 3, 4 and 5 in the Status Register to ‘0’. One
bus write cycle is required to issue the Clear Sta-
tus Register command.
The bits in the Status Register do not automatical-
ly return to ‘0’ when a new Program or Erase com-
mand is issued. The error bits in the Status
Register should be cleared before attempting a
new Program or Erase command.
Program/Erase Suspend Command. The Pro-
gram/Erase Suspend command is used to pause
a Program or Erase operation. One bus write cycle
is required to issue the Program/Erase command
and pause the Program/Erase controller.
During Program/Erase Suspend the Command In-
terface will accept the Program/Erase Resume,
16/64