C8051F300 Datasheet, PDF (84/176 Pages) List of Unclassifed Manufacturers – Mixed Signal ISP Flash MCU Family

C8051F300/1/2/3/4/5
9.7. Flash Error Reset
If a Flash read/write/erase or program read targets an illegal address, a system reset is generated. This
may occur due to any of the following:
• A Flash write or erase is attempted above user code space. This occurs when PSWE is set to ‘1’ and a
MOVX operation is attempted above the user code space address limit.
• A Flash read is attempted above user code space. This occurs when a MOVC operation is attempted
above the user code space address limit.
• A Program read is attempted above user code space. This occurs when user code attempts to branch
to an address above the user code space address limit.
Table 9.1. User Code Space Address Limits
Device
C8051F300/1/2/3
C8051F304
C8051F305
User Code Space Address Limit
0x1DFF
0x0FFF
0x07FF
The FERROR bit (RSTSRC.6) is set following a Flash error reset. The state of the RST pin is unaffected by
this reset.
9.8. Software Reset
Software may force a reset by writing a ‘1’ to the SWRSF bit (RSTSRC.4). The SWRSF bit will read ‘1’ fol-
lowing a software forced reset. The state of the RST pin is unaffected by this reset.
Table 9.2. Reset Electrical Characteristics
–40 to +85 °C unless otherwise specified.
Parameter
Conditions
Min Typ Max Units
RST Output Low Voltage
I_OL = 8.5 mA, V_DD = 2.7 V to
—
—
0.6
V
3.6 V
RST Input High Voltage
RST Input Low Voltage
RST Input Leakage Current
RST = 0.0 V
0.7 x V_DD —
—
V
—
— 0.3 x V_DD
—
25
40
µA
V_DD Monitor Threshold (V_RST)
2.40 2.55 2.70
V
Missing Clock Detector Timeout Time from last system clock ris- 100 220 500
µs
ing edge to reset initiation
Reset Time Delay
Delay between release of any
5.0
—
—
µs
reset source and code execution
at location 0x0000
Minimum RST Low Time to
Generate a System Reset
15
—
—
µs
V_DD Ramp Time
V_DD = 0 to V_RST
—
—
1
ms
84
Rev. 2.8