C8051F300 Datasheet, PDF (66/176 Pages) List of Unclassifed Manufacturers – Mixed Signal ISP Flash MCU Family

C8051F300/1/2/3/4/5
Register
Table 8.3. Special Function Registers* (Continued)
Address
Description
TCON
0x88
Timer/Counter Control
TH0
0x8C
Timer/Counter 0 High
TH1
0x8D
Timer/Counter 1 High
TL0
0x8A
Timer/Counter 0 Low
TL1
0x8B
Timer/Counter 1 Low
TMOD
TMR2RLH
0x89
0xCB
Timer/Counter Mode
Timer/Counter 2 Reload High
TMR2RLL
TMR2H
TMR2L
0xCA
0xCD
0xCC
Timer/Counter 2 Reload Low
Timer/Counter 2 High
Timer/Counter 2 Low
XBR0
XBR1
XBR2
0xE1
0xE2
0xE3
Port I/O Crossbar Control 0
Port I/O Crossbar Control 1
Port I/O Crossbar Control 2
0x97, 0xAE, 0xAF, 0xB4,
0xB6, 0xBF, 0xCE, 0xD2,
0xD3, 0xD4, 0xD5, 0xD6,
0xD7, 0xDD, 0xDE, 0xDF,
0xF5
Reserved
*Note: SFRs are listed in alphabetical order. All undefined SFR locations are reserved
Page
No.
145
148
148
148
148
146
152
152
152
152
105
105
106
8.2.7. Register Descriptions
Following are descriptions of SFRs related to the operation of the CIP-51 System Controller. Reserved bits
should not be set to logic l. Future product versions may use these bits to implement new features in which
case the reset value of the bit will be logic 0, selecting the feature's default state. Detailed descriptions of
the remaining SFRs are included in the sections of the datasheet associated with their corresponding sys-
tem function.
SFR Definition 8.1. DPL: Data Pointer Low Byte
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0 SFR Address:
0x82
Bits7–0: DPL: Data Pointer Low.
The DPL register is the low byte of the 16-bit DPTR. DPTR is used to access indirectly
addressed Flash memory.
66
Rev. 2.8