C8051F300 Datasheet, PDF (79/176 Pages) List of Unclassifed Manufacturers – Mixed Signal ISP Flash MCU Family

C8051F300/1/2/3/4/5
8.4.2. Stop Mode
Setting the Stop Mode Select bit (PCON.1) causes the CIP-51 to enter Stop mode as soon as the instruc-
tion that sets the bit completes execution. In Stop mode the internal oscillator, CPU, and all digital periph-
erals are stopped; the state of the external oscillator circuit is not affected. Each analog peripheral
(including the external oscillator circuit) may be shut down individually prior to entering Stop Mode. Stop
mode can only be terminated by an internal or external reset. On reset, the CIP-51 performs the normal
reset sequence and begins program execution at address 0x0000.
If enabled, the Missing Clock Detector will cause an internal reset and thereby terminate the Stop mode.
The Missing Clock Detector should be disabled if the CPU is to be put to in STOP mode for longer than the
MCD timeout of 100 µsec.
SFR Definition 8.12. PCON: Power Control
R/W
GF5
Bit7
R/W
GF4
Bit6
R/W
GF3
Bit5
R/W
GF2
Bit4
R/W
GF1
Bit3
R/W
GF0
Bit2
R/W
STOP
Bit1
R/W
IDLE
Bit0
Reset Value
00000000
SFR Address:
0x87
Bits7–2:
Bit1:
Bit0:
GF5–GF0: General Purpose Flags 5-0.
These are general purpose flags for use under software control.
STOP: Stop Mode Select.
Setting this bit will place the CIP-51 in Stop mode. This bit will always be read as 0.
1: CPU goes into Stop mode (turns off internal oscillator).
IDLE: Idle Mode Select.
Setting this bit will place the CIP-51 in Idle mode. This bit will always be read as 0.
1: CPU goes into Idle mode (shuts off clock to CPU, but clock to Timers, Interrupts, Serial
Ports, and Analog Peripherals are still active).
Rev. 2.8
79