C8051F300 Datasheet, PDF (119/176 Pages) List of Unclassifed Manufacturers – Mixed Signal ISP Flash MCU Family

C8051F300/1/2/3/4/5
Bit
MASTER
TXMODE
STA
STO
ACKRQ
ARBLOST
ACK
SI
Table 13.3. Sources for Hardware Changes to SMB0CN
Set by Hardware When:
Cleared by Hardware When:
• A START is generated.
• A STOP is generated.
• Arbitration is lost.
• START is generated.
• A START is detected.
• The SMBus interface enters transmitter mode • Arbitration is lost.
(after SMB0DAT is written before the start of • SMB0DAT is not written before the
an SMBus frame).
start of an SMBus frame.
• A START followed by an address byte is
• Must be cleared by software.
received.
• A STOP is detected while addressed as a • A pending STOP is generated.
slave.
• Arbitration is lost due to a detected STOP.
• A byte has been received and an ACK
• After each ACK cycle.
response value is needed.
• A repeated START is detected as a MASTER • Each time SI is cleared.
when STA is low (unwanted repeated START).
• SCL is sensed low while attempting to gener-
ate a STOP or repeated START condition.
• SDA is sensed low while transmitting a ‘1’
(excluding ACK bits).
• The incoming ACK value is low (ACKNOWL- • The incoming ACK value is high (NOT
EDGE).
ACKNOWLEDGE).
• A START has been generated.
• Must be cleared by software.
• Lost arbitration.
• A byte has been transmitted and an
ACK/NACK received.
• A byte has been received.
• A START or repeated START followed by a
slave address + R/W has been received.
• A STOP has been received.
Rev. 2.8
119