C8051F300 Datasheet, PDF (38/176 Pages) List of Unclassifed Manufacturers – Mixed Signal ISP Flash MCU Family

C8051F300/1/2/3/4/5
5.3.2. Tracking Modes
According to Table 5.1 on page 45, each ADC0 conversion must be preceded by a minimum tracking time
for the converted result to be accurate. The AD0TM bit in register ADC0CN controls the ADC0 track-and-
hold mode. In its default state, the ADC0 input is continuously tracked except when a conversion is in
progress. When the AD0TM bit is logic 1, ADC0 operates in low-power track-and-hold mode. In this mode,
each conversion is preceded by a tracking period of 3 SAR clocks (after the start-of-conversion signal).
When the CNVSTR signal is used to initiate conversions in low-power tracking mode, ADC0 tracks only
when CNVSTR is low; conversion begins on the rising edge of CNVSTR (see Figure 5.4). Tracking can
also be disabled (shutdown) when the device is in low power standby or sleep modes. Low-power track-
and-hold mode is also useful when AMUX or PGA settings are frequently changed, due to the settling time
requirements described in Section “5.3.3. Settling Time Requirements” on page 39.
CNVSTR
(AD0CM[2:0]=1xx)
SAR Clocks
A. ADC Timing for External Trigger Source
123456789
AD0TM=1
Low Power
or Convert
Track
Convert
Low Power Mode
AD0TM=0
Track or Convert
Convert
Track
Write '1' to AD0BUSY,
Timer 0, Timer 2, Timer 1 Overflow
(AD0CM[2:0]=000, 001, 010, 011)
B. ADC Timing for Internal Trigger Source
SAR Clocks
AD0TM=1
1 2 3 4 5 6 7 8 9 10 11 12
Low Power
or Convert
Track
Convert
Low Power Mode
SAR Clocks
AD0TM=0
123456789
Track or
Convert
Convert
Track
Figure 5.4. 8-Bit ADC Track and Conversion Example Timing
38
Rev. 2.8