C8051F300 Datasheet, PDF (142/176 Pages) List of Unclassifed Manufacturers – Mixed Signal ISP Flash MCU Family

C8051F300/1/2/3/4/5
The C/T0 bit (TMOD.2) selects the counter/timer's clock source. When C/T0 is set to logic 1, high-to-low
transitions at the selected Timer 0 input pin (T0) increment the timer register (Refer to Section
“12.1. Priority Crossbar Decoder” on page 102 for information on selecting and configuring external I/O
pins). Clearing C/T selects the clock defined by the T0M bit (CKCON.3). When T0M is set, Timer 0 is
clocked by the system clock. When T0M is cleared, Timer 0 is clocked by the source selected by the Clock
Scale bits in CKCON (see SFR Definition 15.3).
Setting the TR0 bit (TCON.4) enables the timer when either GATE0 (TMOD.3) is logic 0 or the input signal
/INT0 is active as defined by bit IN0PL in register IT01CF (see SFR Definition 8.11). Setting GATE0 to ‘1’
allows the timer to be controlled by the external input signal /INT0 (see Section “8.3.5. Interrupt Register
Descriptions” on page 73), facilitating pulse width measurements.
TR0
GATE0
0
X*
1
0
1
1
1
1
*Note: X = Don't Care
/INT0
X*
X*
0
1
Counter/Timer
Disabled
Enabled
Disabled
Enabled
Setting TR0 does not force the timer to reset. The timer registers should be loaded with the desired initial
value before the timer is enabled.
TL1 and TH1 form the 13-bit register for Timer 1 in the same manner as described above for TL0 and TH0.
Timer 1 is configured and controlled using the relevant TCON and TMOD bits just as with Timer 0. The
input signal /INT1 is used with Timer 1; the /INT1 polarity is defined by bit IN1PL in register IT01CF (see
SFR Definition 8.11).
Pre-scaled Clock
SYSCLK
T0
Crossbar
GATE0
CKCON
TTTT SS
2 2 1 0 CC
MMMM A A
HL
10
TMOD
GCT TGCT T
A / 11A / 00
T TMMT TMM
E1 1 0E0 1 0
1
0
IT01CF
IIIIIIII
NNNNNNNN
11110000
PSSSPSSS
LLLLLLLL
210 210
0
0
1
1
TR0
TCLK
TL0
(5 bits)
TH0
(8 bits)
/INT0
IN0PL _XOR
Figure 15.1. T0 Mode 0 Block Diagram
TF1
TR1
TF0
Interrupt
TR0
IE1
IT1
IE0
IT0
142
Rev. 2.8