C8051F300 Datasheet, PDF (114/176 Pages) List of Unclassifed Manufacturers – Mixed Signal ISP Flash MCU Family

C8051F300/1/2/3/4/5
13.4.1. SMBus Configuration Register
The SMBus Configuration register (SMB0CF) is used to enable the SMBus Master and/or Slave modes,
select the SMBus clock source, and select the SMBus timing and timeout options. When the ENSMB bit is
set, the SMBus is enabled for all master and slave events. Slave events may be disabled by setting the
INH bit. With slave events inhibited, the SMBus interface will still monitor the SCL and SDA pins; however,
the interface will NACK all received addresses and will not generate any slave interrupts. When the INH bit
is set, all slave events will be inhibited following the next START (interrupts will continue for the duration of
the current transfer).
Table 13.1. SMBus Clock Source Selection
SMBCS1
0
0
1
1
SMBCS0
SMBus Clock Source
0
Timer 0 Overflow
1
Timer 1 Overflow
0
Timer 2 High Byte Overflow
1
Timer 2 Low Byte Overflow
The SMBCS1-0 bits select the SMBus clock source, which is used only when operating as a master or
when the Free Timeout detection is enabled. When operating as a master, overflows from the selected
source determine the absolute minimum SCL low and high times as defined in Equation 13.1. Note that the
selected clock source may be shared by other peripherals so long as the timer is left running at all times.
For example, Timer 1 overflows may generate the SMBus and UART baud rates simultaneously. Timer
configuration is covered in Section “15. Timers” on page 141.
T_HighMin
=
T_LowMin
=
----------------------1-----------------------
f_{ClockSourceOverflow}
Equation 13.1. Minimum SCL High and Low Times
The selected clock source should be configured to establish the minimum SCL High and Low times as per
Equation 13.1. When the interface is operating as a master (and SCL is not driven or extended by any
other devices on the bus), the typical SMBus bit rate is approximated by Equation 13.2.
BitRate = ^f--^C----^l-^o---^c--^k--^S---^o--^u---^r--^c--^e--^O----^v--^e--^r--^f--^l-^o---^w-
3
Equation 13.2. Typical SMBus Bit Rate
Figure 13.4 shows the typical SCL generation described by Equation 13.2. Notice that T_HIGH is typically
twice as large as T_LOW. The actual SCL output may vary due to other devices on the bus (SCL may be
extended low by slower slave devices, or driven low by contending master devices). The bit rate when
operating as a master will never exceed the limits defined by equation Equation 13.1.
114
Rev. 2.8